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Merge pull request #834 from freechipsproject/resumereq-race

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debug: Fix race between resumereq and resumeack
This commit is contained in:
Megan Wachs 2017-06-29 13:38:20 -07:00 committed by GitHub
commit ae6971b6db
1 changed files with 5 additions and 3 deletions
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8
src/main/scala/uncore/devices/debug/Debug.scala
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@ -540,8 +540,10 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
DMSTATUSRdData.anyrunning := true.B DMSTATUSRdData.anyrunning := true.B
} }
DMSTATUSRdData.allresumeack := ~resumeReqRegs(selectedHartReg) val resumereq = io.innerCtrl.fire() && io.innerCtrl.bits.resumereq
DMSTATUSRdData.anyresumeack := ~resumeReqRegs(selectedHartReg)
DMSTATUSRdData.allresumeack := ~resumeReqRegs(selectedHartReg) && ~resumereq
DMSTATUSRdData.anyresumeack := ~resumeReqRegs(selectedHartReg) && ~resumereq
//TODO //TODO
DMSTATUSRdData.cfgstrvalid := false.B DMSTATUSRdData.cfgstrvalid := false.B
@ -710,7 +712,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
resumeReqRegs(component) := false.B resumeReqRegs(component) := false.B
} }
} }
when(io.innerCtrl.fire() && io.innerCtrl.bits.resumereq) { when(resumereq) {
resumeReqRegs(io.innerCtrl.bits.hartsel) := true.B resumeReqRegs(io.innerCtrl.bits.hartsel) := true.B
} }
} }