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tilelink2: refactor RegField into interface and implementation

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This commit is contained in:
Wesley W. Terpstra
2016-08-31 13:37:20 -07:00
parent d6727abbbc
commit ae2bc4da21
3 changed files with 147 additions and 138 deletions
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6
uncore/src/main/scala/tilelink2/RegisterRouter.scala
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@ -21,8 +21,8 @@ class TLRegisterNode(address: AddressSet, concurrency: Option[Int] = None, beatB
val d = bundleIn(0).d
val edge = edgesIn(0)
val params = RegFieldParams(log2Up(address.mask+1), beatBytes, edge.bundle.sourceBits + edge.bundle.sizeBits)
val in = Wire(Decoupled(new RegFieldInput(params)))
val params = RegMapperParams(log2Up(address.mask+1), beatBytes, edge.bundle.sourceBits + edge.bundle.sizeBits)
val in = Wire(Decoupled(new RegMapperInput(params)))
in.bits.read := a.bits.opcode === TLMessages.Get
in.bits.index := a.bits.address >> log2Ceil(beatBytes)
in.bits.data := a.bits.data
@ -30,7 +30,7 @@ class TLRegisterNode(address: AddressSet, concurrency: Option[Int] = None, beatB
in.bits.extra := Cat(a.bits.source, a.bits.size)
// Invoke the register map builder
val (endIndex, out) = RegFieldHelper(beatBytes, concurrency, in, mapping:_*)
val (endIndex, out) = RegMapper(beatBytes, concurrency, in, mapping:_*)
// All registers must fit inside the device address space
require (address.mask >= (endIndex-1)*beatBytes)