From ae1f7a95f68abfd3dd021f2e1609230684a7b1d6 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 26 Jul 2017 15:09:17 -0700 Subject: [PATCH] Don't nack misses when there's a pending store That effectively increased the miss latency by 5 cycles when there was a store hit followed by a load miss. Since pending stores are drained when releaseInFlight, the check I removed was redundant. --- src/main/scala/rocket/DCache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index b106df2b..204725b2 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -222,7 +222,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val s2_valid_hit_pre_data_ecc = s2_valid_masked && s2_readwrite && !s2_meta_error && s2_hit val s2_valid_data_error = s2_valid_hit_pre_data_ecc && s2_data_error val s2_valid_hit = s2_valid_hit_pre_data_ecc && !s2_data_error - val s2_valid_miss = s2_valid_masked && s2_readwrite && !s2_meta_error && !s2_hit && !any_pstore_valid && !release_ack_wait + val s2_valid_miss = s2_valid_masked && s2_readwrite && !s2_meta_error && !s2_hit && !release_ack_wait val s2_valid_cached_miss = s2_valid_miss && !s2_uncached && !uncachedInFlight.asUInt.orR val s2_victimize = Bool(!usingDataScratchpad) && (s2_valid_cached_miss || s2_valid_data_error || s2_flush_valid) val s2_valid_uncached = s2_valid_miss && s2_uncached