riscv/rocket-chip
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add FPGA memory generator script

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This commit is contained in:
Andrew Waterman
2012-01-13 18:18:48 -08:00
parent acf3134e80
commit addfe55735
2 changed files with 5 additions and 5 deletions
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4
rocket/src/main/scala/icache.scala
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@ -87,7 +87,7 @@ class rocketICacheDM(lines: Int) extends Component {
val tag_array = Mem4(lines, r_cpu_req_ppn);
tag_array.setReadLatency(SRAM_READ_LATENCY);
// tag_array.setTarget('inst);
tag_array.setTarget('inst);
val tag_rdata = tag_array.rw(tag_addr, r_cpu_req_ppn, tag_we);
// valid bit array
@ -108,7 +108,7 @@ class rocketICacheDM(lines: Int) extends Component {
io.cpu.req_idx(PGIDX_BITS-1, offsetmsb-1)).toUFix;
val data_array = Mem4(lines*REFILL_CYCLES, io.mem.resp_data);
data_array.setReadLatency(SRAM_READ_LATENCY);
// data_array.setTarget('inst);
data_array.setTarget('inst);
val data_array_rdata = data_array.rw(data_addr, io.mem.resp_data, io.mem.resp_val);
// output signals