subsystem: pbus crossing type
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@ -11,15 +11,18 @@ import freechips.rocketchip.util._
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case class PeripheryBusParams(
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beatBytes: Int,
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blockBytes: Int,
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arithmeticAtomics: Boolean = true,
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sbusCrossingType: SubsystemClockCrossing = SynchronousCrossing(), // relative to sbus
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frequency: BigInt = BigInt(100000000) // 100 MHz as default bus frequency
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) extends HasTLBusParams
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case object PeripheryBusKey extends Field[PeripheryBusParams]
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class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCrossing = SynchronousCrossing())
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class PeripheryBus(params: PeripheryBusParams)
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(implicit p: Parameters) extends TLBusWrapper(params, "periphery_bus")
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with HasTLXbarPhy
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with HasCrossing {
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val crossing = params.sbusCrossingType
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def toSlave[D,U,E,B <: Data]
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(name: Option[String] = None, buffer: BufferParams = BufferParams.none)
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@ -86,13 +89,11 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
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}
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def fromSystemBus
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(arithmetic: Boolean = true, buffer: BufferParams = BufferParams.default)
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(gen: => TLOutwardNode) {
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def fromSystemBus(gen: => TLOutwardNode) {
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from("sbus") {
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(inwardNode
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:*= TLBuffer(buffer)
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:*= TLAtomicAutomata(arithmetic = arithmetic)
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:*= TLBuffer(BufferParams.default)
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:*= TLAtomicAutomata(arithmetic = params.arithmeticAtomics)
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:*= gen)
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}
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}
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