riscv/rocket-chip
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subsystem: pbus crossing type

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This commit is contained in:
Henry Cook 2018-02-23 13:51:31 -08:00
parent 5725e17969
commit ad823ef43c
1 changed files with 7 additions and 6 deletions
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13
src/main/scala/subsystem/PeripheryBus.scala
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@ -11,15 +11,18 @@ import freechips.rocketchip.util._
case class PeripheryBusParams( case class PeripheryBusParams(
beatBytes: Int, beatBytes: Int,
blockBytes: Int, blockBytes: Int,
arithmeticAtomics: Boolean = true,
sbusCrossingType: SubsystemClockCrossing = SynchronousCrossing(), // relative to sbus
frequency: BigInt = BigInt(100000000) // 100 MHz as default bus frequency frequency: BigInt = BigInt(100000000) // 100 MHz as default bus frequency
) extends HasTLBusParams ) extends HasTLBusParams
case object PeripheryBusKey extends Field[PeripheryBusParams] case object PeripheryBusKey extends Field[PeripheryBusParams]
class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCrossing = SynchronousCrossing()) class PeripheryBus(params: PeripheryBusParams)
(implicit p: Parameters) extends TLBusWrapper(params, "periphery_bus") (implicit p: Parameters) extends TLBusWrapper(params, "periphery_bus")
with HasTLXbarPhy with HasTLXbarPhy
with HasCrossing { with HasCrossing {
val crossing = params.sbusCrossingType
def toSlave[D,U,E,B <: Data] def toSlave[D,U,E,B <: Data]
(name: Option[String] = None, buffer: BufferParams = BufferParams.none) (name: Option[String] = None, buffer: BufferParams = BufferParams.none)
@ -86,13 +89,11 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross
} }
def fromSystemBus def fromSystemBus(gen: => TLOutwardNode) {
(arithmetic: Boolean = true, buffer: BufferParams = BufferParams.default)
(gen: => TLOutwardNode) {
from("sbus") { from("sbus") {
(inwardNode (inwardNode
:*= TLBuffer(buffer) :*= TLBuffer(BufferParams.default)
:*= TLAtomicAutomata(arithmetic = arithmetic) :*= TLAtomicAutomata(arithmetic = params.arithmeticAtomics)
:*= gen) :*= gen)
} }
} }