riscv/rocket-chip
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plic: Fix bit extraction

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This commit is contained in:
Albert Ou 2016-10-06 18:05:03 -07:00
parent b1c777c7a2
commit ad618fd55d
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/uncore/devices/Plic.scala
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@ -141,7 +141,7 @@ class PLIC(val cfg: PLICConfig)(implicit val p: Parameters) extends Module
hart := enableHart hart := enableHart
val word = val word =
if (tlDataBits >= myEnables.size) UInt(0) if (tlDataBits >= myEnables.size) UInt(0)
else addr(log2Ceil((myEnables.size-1)/tlDataBits+1)-1,log2Up(tlDataBytes)) else addr(log2Ceil((myEnables.size-1)/tlDataBits+1) + tlByteAddrBits - 1, tlByteAddrBits)
for (i <- 0 until myEnables.size by tlDataBits) { for (i <- 0 until myEnables.size by tlDataBits) {
when (word === i/tlDataBits) { when (word === i/tlDataBits) {
rdata := Cat(myEnables.slice(i, i + tlDataBits).reverse) rdata := Cat(myEnables.slice(i, i + tlDataBits).reverse)