riscv/rocket-chip
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Reduce cases in which FENCE.I must flush D$

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Memory regions that are uncacheable or have get/put effects should not
reside in the D$, so there is no need to flush them.
This commit is contained in:
Andrew Waterman 2018-01-05 13:58:14 -08:00
parent 206892899f
commit ad0b9a0b1b
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/DCache.scala
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@ -722,7 +722,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
metaArb.io.in(5).bits.data := metaArb.io.in(4).bits.data metaArb.io.in(5).bits.data := metaArb.io.in(4).bits.data
// Only flush D$ on FENCE.I if some cached executable regions are untracked. // Only flush D$ on FENCE.I if some cached executable regions are untracked.
val supports_flush = !edge.manager.managers.forall(m => !m.supportsAcquireT || !m.executable || m.regionType >= RegionType.TRACKED) val supports_flush = !edge.manager.managers.forall(m => !m.supportsAcquireT || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.UNCACHEABLE)
if (supports_flush) { if (supports_flush) {
when (tl_out_a.fire() && !s2_uncached) { flushed := false } when (tl_out_a.fire() && !s2_uncached) { flushed := false }
when (flushing) { when (flushing) {