Move RoCC interface to Diplomacy and TL2 (#807)
* Move RoCC interface to Diplomacy and TL2 * guard rocc arbiter to prevent zero-width wires
This commit is contained in:
Colin Schmidt
GitHub
parent
f1130b2faf
commit
aced18b3bb
@ -165,20 +165,20 @@ class WithNBreakpoints(hwbp: Int) extends Config ((site, here, up) => {
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class WithRoccExample extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(rocc = Seq(
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r.copy(rocc =
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Seq(
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RoCCParams(
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opcodes = OpcodeSet.custom0,
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generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
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generator = (p: Parameters) => LazyModule(new AccumulatorExample()(p))),
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RoCCParams(
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opcodes = OpcodeSet.custom1,
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generator = (p: Parameters) => Module(new TranslatorExample()(p)),
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generator = (p: Parameters) => LazyModule(new TranslatorExample()(p)),
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nPTWPorts = 1),
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RoCCParams(
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opcodes = OpcodeSet.custom2,
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generator = (p: Parameters) => Module(new CharacterCountExample()(p)))
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generator = (p: Parameters) => LazyModule(new CharacterCountExample()(p)))
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))
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}
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case RoccMaxTaggedMemXacts => 1
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})
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class WithDefaultBtb extends Config((site, here, up) => {
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@ -24,7 +24,7 @@ case class RocketTileParams(
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}
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class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p: Parameters) extends BaseTile(rocketParams)(p)
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with CanHaveLegacyRoccs // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache
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with HasLazyRoCC // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache
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with CanHaveScratchpad { // implies CanHavePTW with HasHellaCache with HasICacheFrontend
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nDCachePorts += 1 // core TODO dcachePorts += () => module.core.io.dmem ??
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@ -120,7 +120,7 @@ class RocketTileBundle(outer: RocketTile) extends BaseTileBundle(outer)
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with CanHaveScratchpadBundle
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class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => new RocketTileBundle(outer))
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with CanHaveLegacyRoccsModule
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with HasLazyRoCCModule
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with CanHaveScratchpadModule {
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require(outer.p(PAddrBits) >= outer.masterNode.edgesIn(0).bundle.addressBits,
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@ -136,13 +136,11 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
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dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
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fpuOpt foreach { fpu => core.io.fpu <> fpu.io }
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core.io.ptw <> ptw.io.dpath
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outer.legacyRocc foreach { lr =>
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lr.module.io.core.cmd <> core.io.rocc.cmd
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lr.module.io.core.exception := core.io.rocc.exception
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core.io.rocc.resp <> lr.module.io.core.resp
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core.io.rocc.busy := lr.module.io.core.busy
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core.io.rocc.interrupt := lr.module.io.core.interrupt
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}
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roccCore.cmd <> core.io.rocc.cmd
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roccCore.exception := core.io.rocc.exception
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core.io.rocc.resp <> roccCore.resp
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core.io.rocc.busy := roccCore.busy
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core.io.rocc.interrupt := roccCore.interrupt
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// TODO eliminate this redundancy
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@ -4,159 +4,18 @@
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package tile
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import Chisel._
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import Chisel.ImplicitConversions._
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import config._
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import coreplex._
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import diplomacy._
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import rocket._
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import uncore.constants._
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import uncore.agents._
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import uncore.coherence._
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import uncore.devices._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.util._
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import util._
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case object RoccMaxTaggedMemXacts extends Field[Int]
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case object RoccNMemChannels extends Field[Int]
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case object RoccNPTWPorts extends Field[Int]
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case object BuildRoCC extends Field[Seq[RoCCParams]]
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trait CanHaveLegacyRoccs extends CanHaveSharedFPU with CanHavePTW with HasTileLinkMasterPort {
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val module: CanHaveLegacyRoccsModule
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val legacyRocc = if (p(BuildRoCC).isEmpty) None
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else Some(LazyModule(new LegacyRoccComplex()(p.alter { (site, here, up) => {
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case CacheBlockOffsetBits => log2Up(site(CacheBlockBytes))
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case AmoAluOperandBits => site(XLen)
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case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
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case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
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case TLId => "L1toL2"
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case TLKey("L1toL2") =>
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TileLinkParameters(
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coherencePolicy = new MESICoherence(new NullRepresentation(site(NTiles))),
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nManagers = site(BankedL2Config).nBanks + 1 /* MMIO */,
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nCachingClients = 1,
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nCachelessClients = 1,
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maxClientXacts = List(
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tileParams.dcache.get.nMSHRs + 1 /* IOMSHR */,
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if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)).max,
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maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
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maxManagerXacts = 8,
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dataBeats = (8 * site(CacheBlockBytes)) / site(XLen),
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dataBits = site(CacheBlockBytes)*8)
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}})))
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legacyRocc foreach { lr =>
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tileBus.node :=* lr.masterNode
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nPTWPorts += lr.nPTWPorts
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nDCachePorts += lr.nRocc
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}
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}
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trait CanHaveLegacyRoccsModule extends CanHaveSharedFPUModule
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with CanHavePTWModule
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with HasTileLinkMasterPortModule {
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val outer: CanHaveLegacyRoccs
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fpuOpt foreach { fpu =>
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outer.legacyRocc.orElse {
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fpu.io.cp_req.valid := Bool(false)
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fpu.io.cp_resp.ready := Bool(false)
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None
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} foreach { lr =>
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fpu.io.cp_req <> lr.module.io.fpu.cp_req
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lr.module.io.fpu.cp_resp <> fpu.io.cp_resp
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}
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}
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outer.legacyRocc foreach { lr =>
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ptwPorts ++= lr.module.io.ptw
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dcachePorts ++= lr.module.io.dcache
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}
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}
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class LegacyRoccComplex(implicit p: Parameters) extends LazyModule {
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val buildRocc = p(BuildRoCC)
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val usingRocc = !buildRocc.isEmpty
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val nRocc = buildRocc.size
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val nFPUPorts = buildRocc.filter(_.useFPU).size
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val nMemChannels = buildRocc.map(_.nMemChannels).sum + nRocc
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val nPTWPorts = buildRocc.map(_.nPTWPorts).sum
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val roccOpcodes = buildRocc.map(_.opcodes)
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val masterNode = TLOutputNode()
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val legacies = List.fill(nMemChannels) { LazyModule(new TLLegacy()(p.alterPartial({ case PAddrBits => 32 }))) }
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legacies.foreach { leg => masterNode := TLHintHandler()(leg.node) }
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lazy val module = new LazyModuleImp(this) with HasCoreParameters {
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val io = new Bundle {
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val tl = masterNode.bundleOut
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val dcache = Vec(nRocc, new HellaCacheIO)
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val fpu = new Bundle {
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val cp_req = Decoupled(new FPInput())
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val cp_resp = Decoupled(new FPResult()).flip
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}
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val ptw = Vec(nPTWPorts, new TLBPTWIO)
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val core = new Bundle {
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val cmd = Decoupled(new RoCCCommand).flip
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val resp = Decoupled(new RoCCResponse)
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val busy = Bool(OUTPUT)
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val interrupt = Bool(OUTPUT)
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val exception = Bool(INPUT)
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}
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}
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val respArb = Module(new RRArbiter(new RoCCResponse, nRocc))
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io.core.resp <> respArb.io.out
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val cmdRouter = Module(new RoccCommandRouter(roccOpcodes))
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cmdRouter.io.in <> io.core.cmd
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val roccs = buildRocc.zipWithIndex.map { case (accelParams, i) =>
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val rocc = accelParams.generator(p.alterPartial({
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case RoccNMemChannels => accelParams.nMemChannels
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case RoccNPTWPorts => accelParams.nPTWPorts
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}))
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val dcIF = Module(new SimpleHellaCacheIF)
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rocc.io.cmd <> cmdRouter.io.out(i)
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rocc.io.exception := io.core.exception
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dcIF.io.requestor <> rocc.io.mem
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io.dcache(i) := dcIF.io.cache
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legacies(i).module.io.legacy <> rocc.io.autl
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respArb.io.in(i) <> Queue(rocc.io.resp)
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rocc
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}
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(nRocc until legacies.size) zip roccs.map(_.io.utl) foreach { case(i, utl) =>
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legacies(i).module.io.legacy <> utl
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}
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io.core.busy := cmdRouter.io.busy || roccs.map(_.io.busy).reduce(_ || _)
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io.core.interrupt := roccs.map(_.io.interrupt).reduce(_ || _)
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if (usingFPU && nFPUPorts > 0) {
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val fpArb = Module(new InOrderArbiter(new FPInput, new FPResult, nFPUPorts))
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val fp_rocc_ios = roccs.zip(buildRocc)
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.filter { case (_, params) => params.useFPU }
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.map { case (rocc, _) => rocc.io }
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fpArb.io.in_req <> fp_rocc_ios.map(_.fpu_req)
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fp_rocc_ios.zip(fpArb.io.in_resp).foreach {
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case (rocc, arb) => rocc.fpu_resp <> arb
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}
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io.fpu.cp_req <> fpArb.io.out_req
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fpArb.io.out_resp <> io.fpu.cp_resp
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} else {
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io.fpu.cp_req.valid := Bool(false)
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io.fpu.cp_resp.ready := Bool(false)
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}
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}
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}
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case class RoCCParams(
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opcodes: OpcodeSet,
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generator: Parameters => RoCC,
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nMemChannels: Int = 0,
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generator: Parameters => LazyRoCC,
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nPTWPorts : Int = 0,
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useFPU: Boolean = false)
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@ -195,24 +54,102 @@ class RoCCCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
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override def cloneType = new RoCCCoreIO()(p).asInstanceOf[this.type]
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}
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class RoCCIO(implicit p: Parameters) extends RoCCCoreIO()(p) {
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// These should be handled differently, eventually
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val autl = new ClientUncachedTileLinkIO
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val utl = Vec(p(RoccNMemChannels), new ClientUncachedTileLinkIO)
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/** Base classes for Diplomatic TL2 RoCC units **/
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abstract class LazyRoCC(implicit p: Parameters) extends LazyModule {
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val module: LazyRoCCModule
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val atlNode: TLMixedNode = TLOutputNode()
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val tlNode: TLMixedNode = TLOutputNode()
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}
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class RoCCIO(outer: LazyRoCC)(implicit p: Parameters) extends RoCCCoreIO()(p) {
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val atl = outer.atlNode.bundleOut
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val tl = outer.tlNode.bundleOut
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// Should be handled differently, eventually
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val ptw = Vec(p(RoccNPTWPorts), new TLBPTWIO)
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val fpu_req = Decoupled(new FPInput)
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val fpu_resp = Decoupled(new FPResult).flip
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override def cloneType = new RoCCIO()(p).asInstanceOf[this.type]
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}
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abstract class RoCC(implicit p: Parameters) extends CoreModule()(p) {
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val io = new RoCCIO
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io.mem.req.bits.phys := Bool(true) // don't perform address translation
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io.mem.invalidate_lr := Bool(false) // don't mess with LR/SC
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class LazyRoCCModule(outer: LazyRoCC) extends LazyModuleImp(outer) {
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val io = new RoCCIO(outer)
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}
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class AccumulatorExample(n: Int = 4)(implicit p: Parameters) extends RoCC()(p) {
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/** Mixins for including RoCC **/
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trait HasLazyRoCC extends CanHaveSharedFPU with CanHavePTW with HasTileLinkMasterPort {
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implicit val p: Parameters
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val module: HasLazyRoCCModule
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val roccs = p(BuildRoCC).zipWithIndex.map { case (accelParams, i) =>
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accelParams.generator(p.alterPartial({
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case RoccNPTWPorts => accelParams.nPTWPorts
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}))}
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roccs.map(_.atlNode).foreach { atl => tileBus.node :=* atl }
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roccs.map(_.tlNode).foreach { tl => masterNode :=* tl }
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nPTWPorts += p(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
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nDCachePorts += roccs.size
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}
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trait HasLazyRoCCModule extends CanHaveSharedFPUModule
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with CanHavePTWModule
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with HasCoreParameters
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with HasTileLinkMasterPortModule {
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val outer: HasLazyRoCC
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val roccCore = Wire(new RoCCCoreIO()(outer.p))
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val buildRocc = outer.p(BuildRoCC)
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val usingRocc = !buildRocc.isEmpty
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val nRocc = buildRocc.size
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val nFPUPorts = buildRocc.filter(_.useFPU).size
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val roccOpcodes = buildRocc.map(_.opcodes)
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if(usingRocc) {
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val respArb = Module(new RRArbiter(new RoCCResponse()(outer.p), nRocc))
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roccCore.resp <> respArb.io.out
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val cmdRouter = Module(new RoccCommandRouter(roccOpcodes)(outer.p))
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cmdRouter.io.in <> roccCore.cmd
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outer.roccs.zipWithIndex.foreach { case (rocc, i) =>
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ptwPorts ++= rocc.module.io.ptw
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rocc.module.io.cmd <> cmdRouter.io.out(i)
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rocc.module.io.exception := roccCore.exception
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val dcIF = Module(new SimpleHellaCacheIF()(outer.p))
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dcIF.io.requestor <> rocc.module.io.mem
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dcachePorts += dcIF.io.cache
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respArb.io.in(i) <> Queue(rocc.module.io.resp)
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}
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roccCore.busy := cmdRouter.io.busy || outer.roccs.map(_.module.io.busy).reduce(_ || _)
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roccCore.interrupt := outer.roccs.map(_.module.io.interrupt).reduce(_ || _)
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fpuOpt foreach { fpu =>
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if (usingFPU && nFPUPorts > 0) {
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val fpArb = Module(new InOrderArbiter(new FPInput()(outer.p), new FPResult()(outer.p), nFPUPorts))
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val fp_rocc_ios = outer.roccs.zip(buildRocc)
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.filter { case (_, params) => params.useFPU }
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.map { case (rocc, _) => rocc.module.io }
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fpArb.io.in_req <> fp_rocc_ios.map(_.fpu_req)
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fp_rocc_ios.zip(fpArb.io.in_resp).foreach {
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case (rocc, arb) => rocc.fpu_resp <> arb
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}
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fpu.io.cp_req <> fpArb.io.out_req
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fpArb.io.out_resp <> fpu.io.cp_resp
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} else {
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fpu.io.cp_req.valid := Bool(false)
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fpu.io.cp_resp.ready := Bool(false)
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}
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}
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}
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}
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class AccumulatorExample(implicit p: Parameters) extends LazyRoCC {
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override lazy val module = new AccumulatorExampleModule(this)
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}
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class AccumulatorExampleModule(outer: AccumulatorExample, n: Int = 4)(implicit p: Parameters) extends LazyRoCCModule(outer)
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with HasCoreParameters {
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val regfile = Mem(n, UInt(width = xLen))
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val busy = Reg(init = Vec.fill(n){Bool(false)})
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@ -269,15 +206,19 @@ class AccumulatorExample(n: Int = 4)(implicit p: Parameters) extends RoCC()(p) {
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io.mem.req.valid := cmd.valid && doLoad && !stallReg && !stallResp
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io.mem.req.bits.addr := addend
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io.mem.req.bits.tag := addr
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io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores)
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io.mem.req.bits.cmd := uncore.constants.M_XRD // perform a load (M_XWR for stores)
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io.mem.req.bits.typ := MT_D // D = 8 bytes, W = 4, H = 2, B = 1
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io.mem.req.bits.data := Bits(0) // we're not performing any stores...
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io.autl.acquire.valid := false
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io.autl.grant.ready := false
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io.mem.req.bits.phys := Bool(false)
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io.mem.invalidate_lr := Bool(false)
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}
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class TranslatorExample(implicit p: Parameters) extends RoCC()(p) {
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class TranslatorExample(implicit p: Parameters) extends LazyRoCC {
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override lazy val module = new TranslatorExampleModule(this)
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}
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class TranslatorExampleModule(outer: TranslatorExample)(implicit p: Parameters) extends LazyRoCCModule(outer)
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with HasCoreParameters {
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val req_addr = Reg(UInt(width = coreMaxAddrBits))
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val req_rd = Reg(io.resp.bits.rd)
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val req_offset = req_addr(pgIdxBits - 1, 0)
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@ -316,14 +257,20 @@ class TranslatorExample(implicit p: Parameters) extends RoCC()(p) {
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io.busy := (state =/= s_idle)
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io.interrupt := Bool(false)
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io.mem.req.valid := Bool(false)
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io.autl.acquire.valid := Bool(false)
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io.autl.grant.ready := Bool(false)
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}
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class CharacterCountExample(implicit p: Parameters) extends RoCC()(p)
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with HasTileLinkParameters {
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class CharacterCountExample(implicit p: Parameters) extends LazyRoCC {
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override lazy val module = new CharacterCountExampleModule(this)
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override val atlNode = TLClientNode(TLClientParameters("CharacterCountRoCC"))
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}
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private val blockOffset = tlBeatAddrBits + tlByteAddrBits
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class CharacterCountExampleModule(outer: CharacterCountExample)(implicit p: Parameters) extends LazyRoCCModule(outer)
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with HasCoreParameters
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with HasL1CacheParameters {
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val cacheParams = tileParams.icache.get
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private val blockOffset = blockOffBits
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private val beatOffset = log2Up(cacheDataBits/8)
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val needle = Reg(UInt(width = 8))
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val addr = Reg(UInt(width = coreMaxAddrBits))
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@ -337,18 +284,19 @@ class CharacterCountExample(implicit p: Parameters) extends RoCC()(p)
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val s_idle :: s_acq :: s_gnt :: s_check :: s_resp :: Nil = Enum(Bits(), 5)
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val state = Reg(init = s_idle)
|
||||
|
||||
val gnt = io.autl.grant.bits
|
||||
val recv_data = Reg(UInt(width = tlDataBits))
|
||||
val recv_beat = Reg(UInt(width = tlBeatAddrBits))
|
||||
val tl_out = io.atl.head
|
||||
val gnt = tl_out.d.bits
|
||||
val recv_data = Reg(UInt(width = cacheDataBits))
|
||||
val recv_beat = Reg(UInt(width = log2Up(cacheDataBeats+1)), init = UInt(0))
|
||||
|
||||
val data_bytes = Vec.tabulate(tlDataBytes) { i => recv_data(8 * (i + 1) - 1, 8 * i) }
|
||||
val data_bytes = Vec.tabulate(cacheDataBits/8) { i => recv_data(8 * (i + 1) - 1, 8 * i) }
|
||||
val zero_match = data_bytes.map(_ === UInt(0))
|
||||
val needle_match = data_bytes.map(_ === needle)
|
||||
val first_zero = PriorityEncoder(zero_match)
|
||||
|
||||
val chars_found = PopCount(needle_match.zipWithIndex.map {
|
||||
case (matches, i) =>
|
||||
val idx = Cat(recv_beat, UInt(i, tlByteAddrBits))
|
||||
val idx = Cat(recv_beat - UInt(1), UInt(i, beatOffset))
|
||||
matches && idx >= offset && UInt(i) <= first_zero
|
||||
})
|
||||
val zero_found = zero_match.reduce(_ || _)
|
||||
@ -358,9 +306,12 @@ class CharacterCountExample(implicit p: Parameters) extends RoCC()(p)
|
||||
io.resp.valid := (state === s_resp)
|
||||
io.resp.bits.rd := resp_rd
|
||||
io.resp.bits.data := count
|
||||
io.autl.acquire.valid := (state === s_acq)
|
||||
io.autl.acquire.bits := GetBlock(addr_block = addr_block)
|
||||
io.autl.grant.ready := (state === s_gnt)
|
||||
tl_out.a.valid := (state === s_acq)
|
||||
tl_out.a.bits := outer.atlNode.edgesOut(0).Get(
|
||||
fromSource = UInt(0),
|
||||
toAddress = addr_block << blockOffset,
|
||||
lgSize = UInt(lgCacheBlockBytes))._2
|
||||
tl_out.d.ready := (state === s_gnt)
|
||||
|
||||
when (io.cmd.fire()) {
|
||||
addr := io.cmd.bits.rs1
|
||||
@ -371,10 +322,10 @@ class CharacterCountExample(implicit p: Parameters) extends RoCC()(p)
|
||||
state := s_acq
|
||||
}
|
||||
|
||||
when (io.autl.acquire.fire()) { state := s_gnt }
|
||||
when (tl_out.a.fire()) { state := s_gnt }
|
||||
|
||||
when (io.autl.grant.fire()) {
|
||||
recv_beat := gnt.addr_beat
|
||||
when (tl_out.d.fire()) {
|
||||
recv_beat := recv_beat + UInt(1)
|
||||
recv_data := gnt.data
|
||||
state := s_check
|
||||
}
|
||||
@ -384,7 +335,7 @@ class CharacterCountExample(implicit p: Parameters) extends RoCC()(p)
|
||||
count := count + chars_found
|
||||
}
|
||||
when (zero_found) { finished := Bool(true) }
|
||||
when (recv_beat === UInt(tlDataBeats - 1)) {
|
||||
when (recv_beat === UInt(cacheDataBeats)) {
|
||||
addr := next_addr
|
||||
state := Mux(zero_found || finished, s_resp, s_acq)
|
||||
} .otherwise {
|
||||
@ -397,6 +348,10 @@ class CharacterCountExample(implicit p: Parameters) extends RoCC()(p)
|
||||
io.busy := (state =/= s_idle)
|
||||
io.interrupt := Bool(false)
|
||||
io.mem.req.valid := Bool(false)
|
||||
// Tie off unused channels
|
||||
tl_out.b.ready := Bool(true)
|
||||
tl_out.c.valid := Bool(false)
|
||||
tl_out.e.valid := Bool(false)
|
||||
}
|
||||
|
||||
class OpcodeSet(val opcodes: Seq[UInt]) {
|
||||
@ -14,6 +14,8 @@ package object tilelink2
|
||||
type TLAsyncOutwardNode = OutwardNodeHandle[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]
|
||||
type TLRationalOutwardNode = OutwardNodeHandle[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]
|
||||
type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
|
||||
type TLMixedNode = MixedNode[TLClientPortParameters, TLManagerPortParameters, TLEdgeIn, TLBundle,
|
||||
TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLBundle]
|
||||
|
||||
def OH1ToOH(x: UInt) = (x << 1 | UInt(1)) & ~Cat(UInt(0, width=1), x)
|
||||
def OH1ToUInt(x: UInt) = OHToUInt(OH1ToOH(x))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user