riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Move RoCC interface to Diplomacy and TL2 (#807)

Browse Source 
* Move RoCC interface to Diplomacy and TL2

* guard rocc arbiter to prevent zero-width wires
This commit is contained in:
Colin Schmidt
2017-06-22 12:07:09 -07:00
committed by GitHub
parent f1130b2faf
commit aced18b3bb
4 changed files with 153 additions and 198 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/uncore/tilelink2/package.scala
View File

@ -14,6 +14,8 @@ package object tilelink2
type TLAsyncOutwardNode = OutwardNodeHandle[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]
type TLRationalOutwardNode = OutwardNodeHandle[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]
type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
type TLMixedNode = MixedNode[TLClientPortParameters, TLManagerPortParameters, TLEdgeIn, TLBundle,
TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLBundle]
def OH1ToOH(x: UInt) = (x << 1 | UInt(1)) & ~Cat(UInt(0, width=1), x)
def OH1ToUInt(x: UInt) = OHToUInt(OH1ToOH(x))