riscv/rocket-chip
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Move RoCC interface to Diplomacy and TL2 (#807)

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* Move RoCC interface to Diplomacy and TL2

* guard rocc arbiter to prevent zero-width wires
This commit is contained in:
Colin Schmidt
2017-06-22 12:07:09 -07:00
committed by GitHub
parent f1130b2faf
commit aced18b3bb
4 changed files with 153 additions and 198 deletions
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16
src/main/scala/rocket/RocketTiles.scala
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@ -24,7 +24,7 @@ case class RocketTileParams(
}
class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p: Parameters) extends BaseTile(rocketParams)(p)
with CanHaveLegacyRoccs // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache
with HasLazyRoCC // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache
with CanHaveScratchpad { // implies CanHavePTW with HasHellaCache with HasICacheFrontend
nDCachePorts += 1 // core TODO dcachePorts += () => module.core.io.dmem ??
@ -120,7 +120,7 @@ class RocketTileBundle(outer: RocketTile) extends BaseTileBundle(outer)
with CanHaveScratchpadBundle
class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => new RocketTileBundle(outer))
with CanHaveLegacyRoccsModule
with HasLazyRoCCModule
with CanHaveScratchpadModule {
require(outer.p(PAddrBits) >= outer.masterNode.edgesIn(0).bundle.addressBits,
@ -136,13 +136,11 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
fpuOpt foreach { fpu => core.io.fpu <> fpu.io }
core.io.ptw <> ptw.io.dpath
outer.legacyRocc foreach { lr =>
lr.module.io.core.cmd <> core.io.rocc.cmd
lr.module.io.core.exception := core.io.rocc.exception
core.io.rocc.resp <> lr.module.io.core.resp
core.io.rocc.busy := lr.module.io.core.busy
core.io.rocc.interrupt := lr.module.io.core.interrupt
}
roccCore.cmd <> core.io.rocc.cmd
roccCore.exception := core.io.rocc.exception
core.io.rocc.resp <> roccCore.resp
core.io.rocc.busy := roccCore.busy
core.io.rocc.interrupt := roccCore.interrupt
// TODO eliminate this redundancy