riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Move RoCC interface to Diplomacy and TL2 (#807)

Browse Source 
* Move RoCC interface to Diplomacy and TL2

* guard rocc arbiter to prevent zero-width wires
This commit is contained in:
Colin Schmidt
2017-06-22 12:07:09 -07:00
committed by GitHub
parent f1130b2faf
commit aced18b3bb
4 changed files with 153 additions and 198 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
src/main/scala/coreplex/Configs.scala
View File

@ -165,20 +165,20 @@ class WithNBreakpoints(hwbp: Int) extends Config ((site, here, up) => {
class WithRoccExample extends Config((site, here, up) => {
case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(rocc = Seq(
RoCCParams(
opcodes = OpcodeSet.custom0,
generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
RoCCParams(
opcodes = OpcodeSet.custom1,
generator = (p: Parameters) => Module(new TranslatorExample()(p)),
nPTWPorts = 1),
RoCCParams(
opcodes = OpcodeSet.custom2,
generator = (p: Parameters) => Module(new CharacterCountExample()(p)))
))
}
case RoccMaxTaggedMemXacts => 1
r.copy(rocc =
Seq(
RoCCParams(
opcodes = OpcodeSet.custom0,
generator = (p: Parameters) => LazyModule(new AccumulatorExample()(p))),
RoCCParams(
opcodes = OpcodeSet.custom1,
generator = (p: Parameters) => LazyModule(new TranslatorExample()(p)),
nPTWPorts = 1),
RoCCParams(
opcodes = OpcodeSet.custom2,
generator = (p: Parameters) => LazyModule(new CharacterCountExample()(p)))
))
}
})
class WithDefaultBtb extends Config((site, here, up) => {