From acca0fccf5687fa4eb509ac2b5146cbf05922287 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Wed, 26 Jul 2017 02:13:43 -0700
Subject: [PATCH] Fix BTB not being refilled on some indirect jumps

We are overloading the BTB-hit signal to mean that any part of the frontend
changed the control-flow, not just the BTB.  That's the right thing to do for
most of the control logic, but it means the BTB sometimes won't get refilled
when we'd like it to.  This commit makes the frontend use an invalid BTB entry
number when it, rather than the BTB, changes the control flow.  Since the
entry number is invalid, the BTB will treat it as a miss and refill itself.

This is kind of a hack, but a more palatable fix requires reworking the RVC
IBuf, which I don't have time for right now.
---
 src/main/scala/rocket/BTB.scala      | 7 +++----
 src/main/scala/rocket/Frontend.scala | 1 +
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/rocket/BTB.scala b/src/main/scala/rocket/BTB.scala
index aee91639..656556ec 100644
--- a/src/main/scala/rocket/BTB.scala
+++ b/src/main/scala/rocket/BTB.scala
@@ -11,7 +11,7 @@ import freechips.rocketchip.tile.HasCoreParameters
 import freechips.rocketchip.util._
 
 case class BTBParams(
-  nEntries: Int = 32,
+  nEntries: Int = 30,
   nMatchBits: Int = 14,
   nPages: Int = 6,
   nRAS: Int = 6,
@@ -24,7 +24,6 @@ trait HasBtbParameters extends HasCoreParameters {
   val entries = btbParams.nEntries
   val updatesOutOfOrder = btbParams.updatesOutOfOrder
   val nPages = (btbParams.nPages + 1) / 2 * 2 // control logic assumes 2 divides pages
-  val opaqueBits = log2Up(entries)
 }
 
 abstract class BtbModule(implicit val p: Parameters) extends Module with HasBtbParameters
@@ -141,7 +140,7 @@ class BTBResp(implicit p: Parameters) extends BtbBundle()(p) {
   val mask = Bits(width = fetchWidth)
   val bridx = Bits(width = log2Up(fetchWidth))
   val target = UInt(width = vaddrBits)
-  val entry = UInt(width = opaqueBits)
+  val entry = UInt(width = log2Up(entries + 1))
   val bht = new BHTResp
 }
 
@@ -196,7 +195,7 @@ class BTB(implicit p: Parameters) extends BtbModule {
     if (updatesOutOfOrder) {
       val updateHits = (pageHit << 1)(Mux1H(idxMatch(r_btb_update.bits.pc), idxPages))
       (updateHits.orR, OHToUInt(updateHits))
-    } else (r_btb_update.bits.prediction.valid, r_btb_update.bits.prediction.bits.entry)
+    } else (r_btb_update.bits.prediction.valid && r_btb_update.bits.prediction.bits.entry < entries, r_btb_update.bits.prediction.bits.entry)
 
   val useUpdatePageHit = updatePageHit.orR
   val usePageHit = pageHit.orR
diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala
index db58b854..c7a39274 100644
--- a/src/main/scala/rocket/Frontend.scala
+++ b/src/main/scala/rocket/Frontend.scala
@@ -259,6 +259,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
         when (taken) {
           fq.io.enq.bits.btb.valid := true
           fq.io.enq.bits.btb.bits.taken := true
+          fq.io.enq.bits.btb.bits.entry := UInt(tileParams.btb.get.nEntries)
           s2_redirect := true
         }
       }