riscv/rocket-chip
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Pass D$ backpressure to D-channel, rather than asserting

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This commit is contained in:
Andrew Waterman 2017-07-29 11:48:36 -07:00
parent edcd2c696c
commit ac4339a8e7
1 changed files with 4 additions and 3 deletions
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7
src/main/scala/rocket/DCache.scala
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@ -432,9 +432,10 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
} }
// data refill // data refill
val doRefillBeat = grantIsRefill && tl_out.d.fire() // note this ready-valid signaling ignores E-channel backpressure, which
dataArb.io.in(1).valid := doRefillBeat // benignly means the data RAM might occasionally be redundantly written
assert(dataArb.io.in(1).ready || !doRefillBeat) dataArb.io.in(1).valid := tl_out.d.valid && grantIsRefill && canAcceptCachedGrant
when (grantIsRefill && !dataArb.io.in(1).ready) { tl_out.d.ready := false }
dataArb.io.in(1).bits.write := true dataArb.io.in(1).bits.write := true
dataArb.io.in(1).bits.addr := s2_req_block_addr | d_address_inc dataArb.io.in(1).bits.addr := s2_req_block_addr | d_address_inc
dataArb.io.in(1).bits.way_en := s2_victim_way dataArb.io.in(1).bits.way_en := s2_victim_way