riscv/rocket-chip
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bootrom: move to 0x10000 for more space (DTB on multicore is big)

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Wesley W. Terpstra 2017-03-24 16:00:00 -07:00
parent 34f8ce653a
commit ac205ca10a
4 changed files with 4 additions and 4 deletions
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BIN
bootrom/bootrom.img
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Binary file not shown.

2
bootrom/linker.ld
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@ -1,7 +1,7 @@
SECTIONS
{
DRAM_BASE = 0x80000000;
ROM_BASE = 0x1000;
ROM_BASE = 0x10000;
. = ROM_BASE;
.text.start : { *(.text.start) }

4
src/main/scala/rocketchip/Periphery.scala
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@ -305,8 +305,8 @@ trait PeripheryBootROM {
this: HasTopLevelNetworks =>
val coreplex: CoreplexRISCVPlatform
private val bootrom_address = 0x1000
private val bootrom_size = 0x1000
private val bootrom_address = 0x10000
private val bootrom_size = 0x10000
private lazy val bootrom_contents = GenerateBootROM(coreplex.dtb)
val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))
bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)

2
src/main/scala/rocketchip/RISCVPlatform.scala
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@ -124,5 +124,5 @@ trait HardwiredResetVectorModule extends HasTopLevelNetworksModule {
val outer: HardwiredResetVector
val io: HardwiredResetVectorBundle
outer.coreplex.module.io.resetVector := UInt(0x1040) // boot ROM: hang
outer.coreplex.module.io.resetVector := UInt(0x10040) // boot ROM: hang
}