riscv/rocket-chip
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bootrom: move to 0x10000 for more space (DTB on multicore is big)

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Wesley W. Terpstra committed 2017-03-24 18:18:01 -07:00
1 parent 34f8ce653a
commit ac205ca10a
4 files changed
+4 -4
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src/main/scala/rocketchip/Periphery.scala
+2 -2
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@@ -305,8 +305,8 @@ trait PeripheryBootROM {
this: HasTopLevelNetworks =>
val coreplex: CoreplexRISCVPlatform
private val bootrom_address = 0x1000
private val bootrom_size = 0x1000
private val bootrom_address = 0x10000
private val bootrom_size = 0x10000
private lazy val bootrom_contents = GenerateBootROM(coreplex.dtb)
val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))
bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)