Make BusErrorUnit support 32-bit stores
Otherwise it isn't too useful for RV32!
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@ -44,35 +44,43 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit
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})
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val sources = io.errors.toErrorList
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val mask = sources.map(_.nonEmpty.B).asUInt
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val cause = Reg(init = UInt(0, log2Ceil(sources.lastIndexWhere(_.nonEmpty) + 1)))
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val value = Reg(UInt(width = sources.flatten.map(_.bits.getWidth).max))
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require(value.getWidth <= regWidth)
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val enable = Reg(init = mask)
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val interrupt = Reg(init = UInt(0, sources.size))
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val accrued = Reg(init = UInt(0, sources.size))
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val enable = Reg(init = Vec(sources.map(_.nonEmpty.B)))
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val interrupt = Reg(init = Vec.fill(sources.size)(false.B))
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val accrued = Reg(init = Vec.fill(sources.size)(false.B))
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accrued := accrued | sources.map(_.map(_.valid).getOrElse(false.B)).asUInt
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for ((s, i) <- sources.zipWithIndex; if s.nonEmpty) {
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when (s.get.valid && enable(i) && cause === 0) {
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for ((((s, en), acc), i) <- (sources zip enable zip accrued).zipWithIndex; if s.nonEmpty) {
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when (s.get.valid) {
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acc := true
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when (en && cause === 0) {
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cause := i
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value := s.get.bits
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}
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}
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}
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val (int_out, _) = intNode.out(0)
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io.interrupt := (accrued & interrupt).orR
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io.interrupt := (accrued.asUInt & interrupt.asUInt).orR
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int_out(0) := io.interrupt
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def reg(r: UInt) = RegField(regWidth, r)
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def maskedReg(r: UInt, m: UInt) = RegField(regWidth, r, RegWriteFn((v, d) => { when (v) { r := d & m }; true }))
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def reg(r: UInt) = RegField.bytes(r, (r.getWidth + 7)/8)
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def reg(v: Vec[Bool]) = v.map(r => RegField(1, r))
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def numberRegs(x: Seq[Seq[RegField]]) = x.zipWithIndex.map { case (f, i) => (i * regWidth / 8) -> f }
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node.regmap(
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0 -> Seq(reg(cause),
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node.regmap(numberRegs(Seq(
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reg(cause),
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reg(value),
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maskedReg(enable, mask),
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maskedReg(interrupt, mask),
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maskedReg(accrued, mask)))
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reg(enable),
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reg(interrupt),
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reg(accrued))):_*)
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// hardwire mask bits for unsupported sources to 0
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for ((s, i) <- sources.zipWithIndex; if s.isEmpty) {
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enable(i) := false
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interrupt(i) := false
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accrued(i) := false
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}
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}
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}
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