don't use Scala to Chisel implicit conversions outside of rocket

src/main/scala/coreplex/BaseCoreplex.scala

@@ -148,7 +148,7 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
       tile.interrupts.meip := plic.io.harts(plic.cfg.context(i, 'M'))
       tile.interrupts.seip.foreach(_ := plic.io.harts(plic.cfg.context(i, 'S')))
       tile.interrupts.debug := debugModule.io.debugInterrupts(i)
-      tile.hartid := i
+      tile.hartid := UInt(i)
       tile.resetVector := io.resetVector
     }
 

src/main/scala/rocket/breakpoint.scala

@@ -4,6 +4,7 @@ package rocket
 
 import Chisel._
 import util._
+import Chisel.ImplicitConversions._
 import cde.Parameters
 
 class BPControl(implicit p: Parameters) extends CoreBundle()(p) {

src/main/scala/rocket/btb.scala

@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import cde.{Parameters, Field}
 import util._
+import Chisel.ImplicitConversions._
 import uncore.agents.PseudoLRU
 
 case object BtbKey extends Field[BtbParameters]

src/main/scala/rocket/csr.scala

@@ -7,6 +7,7 @@ import Instructions._
 import cde.{Parameters, Field}
 import uncore.devices._
 import util._
+import Chisel.ImplicitConversions._
 import junctions.AddrMap
 
 class MStatus extends Bundle {
@@ -259,7 +260,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
   val s_interrupts = Mux(!reg_debug && (reg_mstatus.prv < PRV.S || (reg_mstatus.prv === PRV.S && reg_mstatus.sie)), pending_interrupts & reg_mideleg, UInt(0))
   val all_interrupts = m_interrupts | s_interrupts
   val interruptMSB = BigInt(1) << (xLen-1)
-  val interruptCause = interruptMSB + PriorityEncoder(all_interrupts)
+  val interruptCause = UInt(interruptMSB) + PriorityEncoder(all_interrupts)
   io.interrupt := all_interrupts.orR && !io.singleStep || reg_singleStepped
   io.interrupt_cause := interruptCause
   io.bp := reg_bp take nBreakpoints
@@ -267,7 +268,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
   // debug interrupts are only masked by being in debug mode
   when (Bool(usingDebug) && reg_dcsr.debugint && !reg_debug) {
     io.interrupt := true
-    io.interrupt_cause := interruptMSB + CSR.debugIntCause
+    io.interrupt_cause := UInt(interruptMSB) + CSR.debugIntCause
   }
 
   val system_insn = io.rw.cmd === CSR.I
@@ -600,10 +601,10 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
       when (decoded_addr(CSRs.sbadaddr)) { reg_sbadaddr := wdata(vaddrBitsExtended-1,0) }
       when (decoded_addr(CSRs.mideleg))  { reg_mideleg := wdata & delegable_interrupts }
       when (decoded_addr(CSRs.medeleg))  { reg_medeleg := wdata & delegable_exceptions }
-      when (decoded_addr(CSRs.mscounteren)) { reg_mscounteren := wdata & delegable_counters }
+      when (decoded_addr(CSRs.mscounteren)) { reg_mscounteren := wdata & UInt(delegable_counters) }
     }
     if (usingUser) {
-      when (decoded_addr(CSRs.mucounteren)) { reg_mucounteren := wdata & delegable_counters }
+      when (decoded_addr(CSRs.mucounteren)) { reg_mucounteren := wdata & UInt(delegable_counters) }
     }
     if (nBreakpoints > 0) {
       when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata }

src/main/scala/rocket/dcache.scala

@@ -10,6 +10,7 @@ import uncore.coherence._
 import uncore.constants._
 import uncore.util._
 import util._
+import Chisel.ImplicitConversions._
 import cde.{Parameters, Field}
 
 class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {

src/main/scala/rocket/fpu.scala

@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import Instructions._
 import util._
+import Chisel.ImplicitConversions._
 import FPConstants._
 import uncore.constants.MemoryOpConstants._
 import cde.{Parameters, Field}

src/main/scala/rocket/frontend.scala

@@ -3,6 +3,7 @@ package rocket
 import Chisel._
 import uncore.tilelink._
 import util._
+import Chisel.ImplicitConversions._
 import cde.{Parameters, Field}
 
 class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {

src/main/scala/rocket/ibuf.scala

@@ -4,6 +4,7 @@ package rocket
 
 import Chisel._
 import util._
+import Chisel.ImplicitConversions._
 import cde.{Parameters, Field}
 
 class Instruction(implicit val p: Parameters) extends ParameterizedBundle with HasCoreParameters {

src/main/scala/rocket/icache.scala

@@ -5,6 +5,7 @@ import uncore.agents._
 import uncore.tilelink._
 import uncore.util._
 import util._
+import Chisel.ImplicitConversions._
 import cde.{Parameters, Field}
 
 trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {

src/main/scala/rocket/idecode.scala

@@ -8,6 +8,7 @@ import uncore.constants.MemoryOpConstants._
 import ALU._
 import cde.Parameters
 import util._
+import Chisel.ImplicitConversions._
 
 abstract trait DecodeConstants extends HasCoreParameters
 {

src/main/scala/rocket/multiplier.scala

@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import ALU._
 import util._
+import Chisel.ImplicitConversions._
 
 class MultiplierReq(dataBits: Int, tagBits: Int) extends Bundle {
   val fn = Bits(width = SZ_ALU_FN)

src/main/scala/rocket/nbdcache.scala

@@ -9,6 +9,7 @@ import uncore.agents._
 import uncore.constants._
 import uncore.util._
 import util._
+import Chisel.ImplicitConversions._
 import cde.{Parameters, Field}
 
 case class DCacheConfig(

src/main/scala/rocket/package.scala

@@ -1,4 +1,3 @@
 // See LICENSE for license details.
 
-package object rocket extends 
-  rocket.constants.ScalarOpConstants
+package object rocket extends rocket.constants.ScalarOpConstants

src/main/scala/rocket/ptw.scala

@@ -6,6 +6,7 @@ import Chisel._
 import uncore.agents._
 import uncore.constants._
 import util._
+import Chisel.ImplicitConversions._
 import cde.{Parameters, Field}
 
 class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {

src/main/scala/rocket/rocc.scala

@@ -7,6 +7,7 @@ import uncore.tilelink._
 import uncore.constants._
 import uncore.agents.CacheName
 import util._
+import Chisel.ImplicitConversions._
 import cde.{Parameters, Field}
 
 case object RoccMaxTaggedMemXacts extends Field[Int]

src/main/scala/rocket/rocket.scala

@@ -8,6 +8,7 @@ import uncore.agents.CacheName
 import uncore.constants._
 import junctions.HasAddrMapParameters
 import util._
+import Chisel.ImplicitConversions._
 import cde.{Parameters, Field}
 
 case object XLen extends Field[Int]

src/main/scala/rocket/tlb.scala

@@ -4,6 +4,7 @@ package rocket
 
 import Chisel._
 import util._
+import Chisel.ImplicitConversions._
 import junctions._
 import scala.math._
 import cde.{Parameters, Field}

src/main/scala/rocketchip/TestHarness.scala

@@ -4,9 +4,9 @@ package rocketchip
 
 import Chisel._
 import cde.{Parameters, Field}
-import util._
 import junctions._
 import junctions.NastiConstants._
+import util.LatencyPipe
 
 case object BuildExampleTop extends Field[Parameters => ExampleTop]
 case object SimMemLatency extends Field[Int]
@@ -31,7 +31,7 @@ class TestHarness(q: Parameters) extends Module {
   require(dut.io.mmio_tl.isEmpty)
 
   for (int <- dut.io.interrupts)
-    int := false
+    int := Bool(false)
 
   if (dut.io.mem_axi.nonEmpty) {
     val memSize = p(GlobalAddrMap)("mem").size
@@ -82,12 +82,12 @@ class SimAXIMem(size: BigInt)(implicit p: Parameters) extends NastiModule()(p) {
   val rValid = Reg(init = Bool(false))
   val ar = RegEnable(io.axi.ar.bits, io.axi.ar.fire())
   io.axi.ar.ready := !rValid
-  when (io.axi.ar.fire()) { rValid := true }
+  when (io.axi.ar.fire()) { rValid := Bool(true) }
   when (io.axi.r.fire()) {
     assert(ar.burst === NastiConstants.BURST_INCR)
     ar.addr := ar.addr + (UInt(1) << ar.size)
-    ar.len := ar.len - 1
-    when (ar.len === UInt(0)) { rValid := false }
+    ar.len := ar.len - UInt(1)
+    when (ar.len === UInt(0)) { rValid := Bool(false) }
   }
 
   val w = io.axi.w.bits
@@ -100,15 +100,15 @@ class SimAXIMem(size: BigInt)(implicit p: Parameters) extends NastiModule()(p) {
   val aw = RegEnable(io.axi.aw.bits, io.axi.aw.fire())
   io.axi.aw.ready := !wValid && !bValid
   io.axi.w.ready := wValid
-  when (io.axi.b.fire()) { bValid := false }
-  when (io.axi.aw.fire()) { wValid := true }
+  when (io.axi.b.fire()) { bValid := Bool(false) }
+  when (io.axi.aw.fire()) { wValid := Bool(true) }
   when (io.axi.w.fire()) {
     assert(aw.burst === NastiConstants.BURST_INCR)
     aw.addr := aw.addr + (UInt(1) << aw.size)
-    aw.len := aw.len - 1
+    aw.len := aw.len - UInt(1)
     when (aw.len === UInt(0)) {
-      wValid := false
-      bValid := true
+      wValid := Bool(false)
+      bValid := Bool(true)
     }
 
     def row = mem((aw.addr >> log2Ceil(nastiXDataBits/8))(log2Ceil(depth)-1, 0))
@@ -142,9 +142,9 @@ class SimDTM(implicit p: Parameters) extends BlackBox {
     io.reset := tbreset
     dutio <> io.debug
 
-    tbsuccess := dutsuccess || io.exit === 1
-    when (io.exit >= 2) {
-      printf("*** FAILED *** (exit code = %d)\n", io.exit >> 1)
+    tbsuccess := dutsuccess || io.exit === UInt(1)
+    when (io.exit >= UInt(2)) {
+      printf("*** FAILED *** (exit code = %d)\n", io.exit >> UInt(1))
       stop(1)
     }
   }

src/main/scala/uncore/devices/Prci.scala

@@ -52,7 +52,7 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep
 
   val time = Seq.fill(timeWidth/regWidth)(Reg(init=UInt(0, width = regWidth)))
   when (io.rtcTick) {
-    val newTime = time.asUInt + 1
+    val newTime = time.asUInt + UInt(1)
     for ((reg, i) <- time zip (0 until timeWidth by regWidth))
       reg := newTime >> i
   }

src/main/scala/util/Misc.scala

@@ -135,5 +135,5 @@ object Random
   private def round(x: Double): Int =
     if (x.toInt.toDouble == x) x.toInt else (x.toInt + 1) & -2
   private def partition(value: UInt, slices: Int) =
-    Seq.tabulate(slices)(i => value < round((i << value.getWidth).toDouble / slices))
+    Seq.tabulate(slices)(i => value < UInt(round((i << value.getWidth).toDouble / slices)))
 }

src/main/scala/util/Package.scala

@@ -22,10 +22,6 @@ package object util {
   }
 
   implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
-  implicit def intToUInt(x: Int): UInt = UInt(x)
-  implicit def bigIntToUInt(x: BigInt): UInt = UInt(x)
-  implicit def booleanToBool(x: Boolean): Bits = Bool(x)
-  implicit def intSeqToUIntSeq(x: Seq[Int]): Seq[UInt] = x.map(UInt(_))
   implicit def wcToUInt(c: WideCounter): UInt = c.value
 
   implicit class UIntToAugmentedUInt(val x: UInt) extends AnyVal {