don't use Scala to Chisel implicit conversions outside of rocket

src/main/scala/uncore/devices/Prci.scala

@@ -52,7 +52,7 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep
 
   val time = Seq.fill(timeWidth/regWidth)(Reg(init=UInt(0, width = regWidth)))
   when (io.rtcTick) {
-    val newTime = time.asUInt + 1
+    val newTime = time.asUInt + UInt(1)
     for ((reg, i) <- time zip (0 until timeWidth by regWidth))
       reg := newTime >> i
   }