don't use Scala to Chisel implicit conversions outside of rocket

src/main/scala/rocket/breakpoint.scala

@@ -4,6 +4,7 @@ package rocket
 
 import Chisel._
 import util._
+import Chisel.ImplicitConversions._
 import cde.Parameters
 
 class BPControl(implicit p: Parameters) extends CoreBundle()(p) {

src/main/scala/rocket/btb.scala

@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import cde.{Parameters, Field}
 import util._
+import Chisel.ImplicitConversions._
 import uncore.agents.PseudoLRU
 
 case object BtbKey extends Field[BtbParameters]

src/main/scala/rocket/csr.scala

@@ -7,6 +7,7 @@ import Instructions._
 import cde.{Parameters, Field}
 import uncore.devices._
 import util._
+import Chisel.ImplicitConversions._
 import junctions.AddrMap
 
 class MStatus extends Bundle {
@@ -259,7 +260,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
   val s_interrupts = Mux(!reg_debug && (reg_mstatus.prv < PRV.S || (reg_mstatus.prv === PRV.S && reg_mstatus.sie)), pending_interrupts & reg_mideleg, UInt(0))
   val all_interrupts = m_interrupts | s_interrupts
   val interruptMSB = BigInt(1) << (xLen-1)
-  val interruptCause = interruptMSB + PriorityEncoder(all_interrupts)
+  val interruptCause = UInt(interruptMSB) + PriorityEncoder(all_interrupts)
   io.interrupt := all_interrupts.orR && !io.singleStep || reg_singleStepped
   io.interrupt_cause := interruptCause
   io.bp := reg_bp take nBreakpoints
@@ -267,7 +268,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
   // debug interrupts are only masked by being in debug mode
   when (Bool(usingDebug) && reg_dcsr.debugint && !reg_debug) {
     io.interrupt := true
-    io.interrupt_cause := interruptMSB + CSR.debugIntCause
+    io.interrupt_cause := UInt(interruptMSB) + CSR.debugIntCause
   }
 
   val system_insn = io.rw.cmd === CSR.I
@@ -600,10 +601,10 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
       when (decoded_addr(CSRs.sbadaddr)) { reg_sbadaddr := wdata(vaddrBitsExtended-1,0) }
       when (decoded_addr(CSRs.mideleg))  { reg_mideleg := wdata & delegable_interrupts }
       when (decoded_addr(CSRs.medeleg))  { reg_medeleg := wdata & delegable_exceptions }
-      when (decoded_addr(CSRs.mscounteren)) { reg_mscounteren := wdata & delegable_counters }
+      when (decoded_addr(CSRs.mscounteren)) { reg_mscounteren := wdata & UInt(delegable_counters) }
     }
     if (usingUser) {
-      when (decoded_addr(CSRs.mucounteren)) { reg_mucounteren := wdata & delegable_counters }
+      when (decoded_addr(CSRs.mucounteren)) { reg_mucounteren := wdata & UInt(delegable_counters) }
     }
     if (nBreakpoints > 0) {
       when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata }

src/main/scala/rocket/dcache.scala

@@ -10,6 +10,7 @@ import uncore.coherence._
 import uncore.constants._
 import uncore.util._
 import util._
+import Chisel.ImplicitConversions._
 import cde.{Parameters, Field}
 
 class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {

src/main/scala/rocket/fpu.scala

@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import Instructions._
 import util._
+import Chisel.ImplicitConversions._
 import FPConstants._
 import uncore.constants.MemoryOpConstants._
 import cde.{Parameters, Field}

src/main/scala/rocket/frontend.scala

@@ -3,6 +3,7 @@ package rocket
 import Chisel._
 import uncore.tilelink._
 import util._
+import Chisel.ImplicitConversions._
 import cde.{Parameters, Field}
 
 class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {

src/main/scala/rocket/ibuf.scala

@@ -4,6 +4,7 @@ package rocket
 
 import Chisel._
 import util._
+import Chisel.ImplicitConversions._
 import cde.{Parameters, Field}
 
 class Instruction(implicit val p: Parameters) extends ParameterizedBundle with HasCoreParameters {

src/main/scala/rocket/icache.scala

@@ -5,6 +5,7 @@ import uncore.agents._
 import uncore.tilelink._
 import uncore.util._
 import util._
+import Chisel.ImplicitConversions._
 import cde.{Parameters, Field}
 
 trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {

src/main/scala/rocket/idecode.scala

@@ -8,6 +8,7 @@ import uncore.constants.MemoryOpConstants._
 import ALU._
 import cde.Parameters
 import util._
+import Chisel.ImplicitConversions._
 
 abstract trait DecodeConstants extends HasCoreParameters
 {

src/main/scala/rocket/multiplier.scala

@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import ALU._
 import util._
+import Chisel.ImplicitConversions._
 
 class MultiplierReq(dataBits: Int, tagBits: Int) extends Bundle {
   val fn = Bits(width = SZ_ALU_FN)

src/main/scala/rocket/nbdcache.scala

@@ -9,6 +9,7 @@ import uncore.agents._
 import uncore.constants._
 import uncore.util._
 import util._
+import Chisel.ImplicitConversions._
 import cde.{Parameters, Field}
 
 case class DCacheConfig(

src/main/scala/rocket/package.scala

@@ -1,4 +1,3 @@
 // See LICENSE for license details.
 
-package object rocket extends 
-  rocket.constants.ScalarOpConstants
+package object rocket extends rocket.constants.ScalarOpConstants

src/main/scala/rocket/ptw.scala

@@ -6,6 +6,7 @@ import Chisel._
 import uncore.agents._
 import uncore.constants._
 import util._
+import Chisel.ImplicitConversions._
 import cde.{Parameters, Field}
 
 class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {

src/main/scala/rocket/rocc.scala

@@ -7,6 +7,7 @@ import uncore.tilelink._
 import uncore.constants._
 import uncore.agents.CacheName
 import util._
+import Chisel.ImplicitConversions._
 import cde.{Parameters, Field}
 
 case object RoccMaxTaggedMemXacts extends Field[Int]

src/main/scala/rocket/rocket.scala

@@ -8,6 +8,7 @@ import uncore.agents.CacheName
 import uncore.constants._
 import junctions.HasAddrMapParameters
 import util._
+import Chisel.ImplicitConversions._
 import cde.{Parameters, Field}
 
 case object XLen extends Field[Int]

src/main/scala/rocket/tlb.scala

@@ -4,6 +4,7 @@ package rocket
 
 import Chisel._
 import util._
+import Chisel.ImplicitConversions._
 import junctions._
 import scala.math._
 import cde.{Parameters, Field}