From 7da65434ee44682df4d0901e6abbfe87a7d0b6a9 Mon Sep 17 00:00:00 2001 From: Stephen Twigg Date: Wed, 30 Oct 2013 20:44:02 -0700 Subject: [PATCH 01/28] Initial commit for the hwacha reference-chip/rocket re-integration. --- project/build.scala | 3 ++- src/main/scala/RocketChip.scala | 5 ++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/project/build.scala b/project/build.scala index 5bf99b3c..9f244687 100644 --- a/project/build.scala +++ b/project/build.scala @@ -29,7 +29,8 @@ object BuildSettings extends Build { lazy val hardfloat = Project("hardfloat", file("hardfloat"), settings = buildSettings) dependsOn(chisel) lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(hardfloat) lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore) - lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket) + lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(uncore, rocket) + lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha) val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code") val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command") diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index d282d2b0..f80411b2 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -254,8 +254,11 @@ class Top extends Module { val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16) val dc = DCacheConfig(128, 4, ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates) + val hc = hwacha.HwachaConfiguration(8, 256) val rc = RocketConfiguration(tl, ic, dc, - fpu = HAS_FPU) + fpu = HAS_FPU, + rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c)) + ) val io = new VLSITopIO(HTIF_WIDTH) From 3cdfde9861dbdc3ad579b602aea7d86332134e8c Mon Sep 17 00:00:00 2001 From: Stephen Twigg Date: Tue, 5 Nov 2013 15:31:59 -0800 Subject: [PATCH 02/28] Push hwacha, rocket --- rocket | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket b/rocket index b1012b25..b246050b 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit b1012b251061631fe00bcdd5327a1e2fba1e6f61 +Subproject commit b246050b7de0d5610e59ec9dbdd3839759e354f9 From c8108477615c61e0e8e6545b38be5aecf9bbb1fa Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 5 Nov 2013 17:12:25 -0800 Subject: [PATCH 03/28] hookup all memory ports --- rocket | 2 +- src/main/scala/RocketChip.scala | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/rocket b/rocket index b246050b..02da61cc 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit b246050b7de0d5610e59ec9dbdd3839759e354f9 +Subproject commit 02da61cc09e674ca9a5f9baaeac580d30cf7d693 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index f80411b2..c8444ca2 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -254,7 +254,8 @@ class Top extends Module { val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16) val dc = DCacheConfig(128, 4, ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates) - val hc = hwacha.HwachaConfiguration(8, 256) + val vic = ICacheConfig(128, 1) + val hc = hwacha.HwachaConfiguration(vic, 8, 256, ndtlb = 8, nptlb = 2) val rc = RocketConfiguration(tl, ic, dc, fpu = HAS_FPU, rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c)) From a870f51300fa0bc4be34fd3c6ce4fe3fbfe0e208 Mon Sep 17 00:00:00 2001 From: Stephen Twigg Date: Thu, 14 Nov 2013 15:56:25 -0800 Subject: [PATCH 04/28] Add some vector tests --- Makefrag | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Makefrag b/Makefrag index 2afc2d7f..509c6844 100644 --- a/Makefrag +++ b/Makefrag @@ -212,6 +212,9 @@ vecasm_p_tests = \ rv64uv-p-utidx \ rv64uv-p-vmsv \ rv64uv-p-vmvv \ + rv64uv-p-vsetcfg \ + rv64uv-p-vsetcfgi \ + rv64uv-p-vsetvl \ rv64uv-p-vfmvv \ rv64uv-p-movz \ rv64uv-p-movn \ From 36e715a79764c33ebeaaf18e5e5bed2eed027f28 Mon Sep 17 00:00:00 2001 From: Stephen Twigg Date: Thu, 14 Nov 2013 15:56:51 -0800 Subject: [PATCH 05/28] Use newer version of hwacha (still not quite working but no longer stalls) --- riscv-tests | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-tests b/riscv-tests index 532db85c..ecd97be4 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit 532db85c68d3517ed46f2d9203a3e72db5c8dec3 +Subproject commit ecd97be4c4993b586cd15b5096ab614142fe4db4 From d7c6824c5103645a9602d765370291c238944ab8 Mon Sep 17 00:00:00 2001 From: Stephen Twigg Date: Mon, 18 Nov 2013 13:30:02 -0800 Subject: [PATCH 06/28] Push riscv-tests and riscv-tools --- riscv-tests | 2 +- riscv-tools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv-tests b/riscv-tests index ecd97be4..c2d41351 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit ecd97be4c4993b586cd15b5096ab614142fe4db4 +Subproject commit c2d41351c42fe8e78c24f27ac5f0d0b6d1c87516 diff --git a/riscv-tools b/riscv-tools index 17a9427f..3705cef8 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 17a9427f93b7319c5e27051bbd6d4d3b8026f70c +Subproject commit 3705cef8590cea7624749755f2740cda66a8aeae From c06299c96369951594f4754958d3b2f4e91d1a84 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 19 Nov 2013 18:01:59 -0800 Subject: [PATCH 07/28] push tests --- riscv-tests | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-tests b/riscv-tests index c2d41351..59127ea6 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit c2d41351c42fe8e78c24f27ac5f0d0b6d1c87516 +Subproject commit 59127ea6ea04954673a763505b9b62730dc049ed From 3eafbbd1e2e907316c9dee14299f8099930996d4 Mon Sep 17 00:00:00 2001 From: Stephen Twigg Date: Tue, 19 Nov 2013 22:14:11 -0800 Subject: [PATCH 08/28] Push hwacha, rocket. All physical tests pass. --- rocket | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket b/rocket index 2728029c..9b0b6a1d 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 2728029ceb287ac528428ed0f726c193ffcc4133 +Subproject commit 9b0b6a1dc914b60d8a832664e4e9ead43646f38e From 56421948341052791c8136d9f30e0df09f03b30b Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Wed, 20 Nov 2013 16:44:33 -0800 Subject: [PATCH 09/28] push hwacha to consistent state --- Makefrag | 25 +++++++++++++------------ riscv-tests | 2 +- uncore | 2 +- 3 files changed, 15 insertions(+), 14 deletions(-) diff --git a/Makefrag b/Makefrag index 509c6844..2e638532 100644 --- a/Makefrag +++ b/Makefrag @@ -215,7 +215,6 @@ vecasm_p_tests = \ rv64uv-p-vsetcfg \ rv64uv-p-vsetcfgi \ rv64uv-p-vsetvl \ - rv64uv-p-vfmvv \ rv64uv-p-movz \ rv64uv-p-movn \ rv64uv-p-fmovz \ @@ -242,21 +241,23 @@ vecasm_p_tests = \ rv64uv-p-vvadd_w \ rv64uv-p-vvmul_d \ rv64uv-p-amoadd_d \ - rv64uv-p-amoswap_d \ rv64uv-p-amoand_d \ rv64uv-p-amoor_d \ + rv64uv-p-amoxor_d \ rv64uv-p-amomax_d \ rv64uv-p-amomin_d \ rv64uv-p-amomaxu_d \ rv64uv-p-amominu_d \ + rv64uv-p-amoswap_d \ rv64uv-p-amoadd_w \ - rv64uv-p-amoswap_w \ rv64uv-p-amoand_w \ rv64uv-p-amoor_w \ + rv64uv-p-amoxor_w \ rv64uv-p-amomax_w \ rv64uv-p-amomin_w \ rv64uv-p-amomaxu_w \ rv64uv-p-amominu_w \ + rv64uv-p-amoswap_w \ rv64uv-p-imul \ rv64uv-p-fma \ rv64ui-p-vec-mul \ @@ -300,15 +301,15 @@ vecasm_p_tests = \ rv64uf-p-vec-fcvt_w \ rv64uf-p-vec-fcvt \ rv64uf-p-vec-fcmp \ - rv64sv-p-illegal_tvec_cmd \ - rv64sv-p-illegal_tvec_regid \ - rv64sv-p-illegal_vt_inst \ - rv64sv-p-illegal_vt_regid \ - rv64sv-p-ma_utld \ - rv64sv-p-ma_utsd \ - rv64sv-p-ma_vld \ - rv64sv-p-ma_vsd \ - rv64sv-p-ma_vt_inst \ +# rv64sv-p-illegal_tvec_cmd \ +# rv64sv-p-illegal_tvec_regid \ +# rv64sv-p-illegal_vt_inst \ +# rv64sv-p-illegal_vt_regid \ +# rv64sv-p-ma_utld \ +# rv64sv-p-ma_utsd \ +# rv64sv-p-ma_vld \ +# rv64sv-p-ma_vsd \ +# rv64sv-p-ma_vt_inst \ vecasm_v_tests = \ rv64uv-v-wakeup \ diff --git a/riscv-tests b/riscv-tests index 59127ea6..fdf5e6f9 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit 59127ea6ea04954673a763505b9b62730dc049ed +Subproject commit fdf5e6f97d53722d7ec44c4591f1ab740a092808 diff --git a/uncore b/uncore index 9eadc3d8..ac4a5373 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 9eadc3d8c87507fbc8981d3ff9a7490ab8a35851 +Subproject commit ac4a5373c69c04a003bebe54fb7eca7387a43e4d From 1c6f4e91f93886cb76775aafc0163a2f6221f2ef Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Thu, 21 Nov 2013 15:02:40 -0800 Subject: [PATCH 10/28] merge origin/master, and push hwacha --- riscv-tools | 2 +- rocket | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv-tools b/riscv-tools index 3705cef8..e5307451 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 3705cef8590cea7624749755f2740cda66a8aeae +Subproject commit e5307451589e339c56e54e869bdb1d74c6cb8e90 diff --git a/rocket b/rocket index 9b0b6a1d..b0ac6926 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 9b0b6a1dc914b60d8a832664e4e9ead43646f38e +Subproject commit b0ac69269508a78babd4f79c824dbd9d5fec030e From 37b86c89fafb14a4d8e886c53219e9a4552b148e Mon Sep 17 00:00:00 2001 From: Quan Nguyen Date: Fri, 13 Dec 2013 03:38:16 -0800 Subject: [PATCH 11/28] Introduce confprec --- hardfloat | 2 +- riscv-tools | 2 +- rocket | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hardfloat b/hardfloat index def6363b..ac7ec37a 160000 --- a/hardfloat +++ b/hardfloat @@ -1 +1 @@ -Subproject commit def6363b442dc1c8b386d9e9d3c19edad54313f3 +Subproject commit ac7ec37adf725caf9291d813e46826a9a7cab22c diff --git a/riscv-tools b/riscv-tools index e5307451..20b2d997 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit e5307451589e339c56e54e869bdb1d74c6cb8e90 +Subproject commit 20b2d997f01a3c879b0158ab1af3f4947628bb36 diff --git a/rocket b/rocket index b0ac6926..5555e6f7 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit b0ac69269508a78babd4f79c824dbd9d5fec030e +Subproject commit 5555e6f7485387ed8fba69c6ae3935fabdf8c6e3 From ee0c4ca291076baef7944071d76fe82d42de7e43 Mon Sep 17 00:00:00 2001 From: Stephen Twigg Date: Tue, 21 Jan 2014 14:48:04 -0800 Subject: [PATCH 12/28] Push chisel, rocket, hwacha, tools, tests to incorporate a bunch of new changes (ISA alterations) --- chisel | 2 +- csrc/emulator.cc | 2 +- riscv-tests | 2 +- riscv-tools | 2 +- rocket | 2 +- src/main/scala/RocketChip.scala | 2 +- src/main/scala/fpga.scala | 2 +- uncore | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/chisel b/chisel index 4483d414..ae1d1de8 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 4483d41471e4cb8e77b61f3f13255f4d59425d61 +Subproject commit ae1d1de82188f0a1d79a4e8eb613743942a13eb3 diff --git a/csrc/emulator.cc b/csrc/emulator.cc index 3765e161..587036b9 100644 --- a/csrc/emulator.cc +++ b/csrc/emulator.cc @@ -125,7 +125,7 @@ int main(int argc, char** argv) } if (log) - tile.print(stderr); + tile.print(stderr, stderr); if (vcd) tile.dump(vcdfile, trace_count); diff --git a/riscv-tests b/riscv-tests index fdf5e6f9..7356626e 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit fdf5e6f97d53722d7ec44c4591f1ab740a092808 +Subproject commit 7356626efe5c331f77202e6e1d875c85c4b4588a diff --git a/riscv-tools b/riscv-tools index 20b2d997..323639fa 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 20b2d997f01a3c879b0158ab1af3f4947628bb36 +Subproject commit 323639fa2ae51fbc60c655d2a16611672809beef diff --git a/rocket b/rocket index 5555e6f7..9aa03938 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 5555e6f7485387ed8fba69c6ae3935fabdf8c6e3 +Subproject commit 9aa03938c05323e292c79b8b5fb4a49e911183d7 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 7733067c..083220d8 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -157,7 +157,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf val mem_backup = new ioMemSerialized(htif_width) val mem_backup_en = Bool(INPUT) } - val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR)) + val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR)) val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif)) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) outmemsys.io.incoherent := incoherentWithHtif diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index 3aab9d29..e491caba 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -45,7 +45,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput } - val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR)) + val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR)) val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif)) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) outmemsys.io.incoherent := incoherentWithHtif diff --git a/uncore b/uncore index ac4a5373..a5826575 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit ac4a5373c69c04a003bebe54fb7eca7387a43e4d +Subproject commit a58265755fcb90aebe5377cb9b7343732fd14b9a From ce36d67f05d890b0081cd86b59b74a168722c818 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Wed, 22 Jan 2014 20:18:44 -0800 Subject: [PATCH 13/28] push tools/tests --- riscv-tests | 2 +- riscv-tools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv-tests b/riscv-tests index 7356626e..a4815615 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit 7356626efe5c331f77202e6e1d875c85c4b4588a +Subproject commit a481561500f43c8a022cfc0ba1695914e1df4d57 diff --git a/riscv-tools b/riscv-tools index 323639fa..ace38a2b 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 323639fa2ae51fbc60c655d2a16611672809beef +Subproject commit ace38a2b39f44be4630ca64d331be49be63f15b0 From fb827abbfa18223daaecc80ea8416e749a33f43c Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 28 Jan 2014 03:50:07 -0800 Subject: [PATCH 14/28] Use dynamic fesvr library --- chisel | 2 +- emulator/Makefile | 2 +- riscv-tests | 2 +- rocket | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/chisel b/chisel index ae1d1de8..3b1979d8 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit ae1d1de82188f0a1d79a4e8eb613743942a13eb3 +Subproject commit 3b1979d8a182d9fa8a65ce0523581f353f9f4603 diff --git a/emulator/Makefile b/emulator/Makefile index b598cc22..674c88a0 100644 --- a/emulator/Makefile +++ b/emulator/Makefile @@ -10,7 +10,7 @@ CXXFLAGS := $(CXXFLAGS) -std=c++11 -I$(RISCV)/include CXXSRCS := emulator disasm mm mm_dramsim2 CXXFLAGS := $(CXXFLAGS) -I$(base_dir)/csrc -I$(base_dir)/dramsim2 -LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -L. -ldramsim -lfesvr -lpthread +LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L. -ldramsim -lfesvr -lpthread OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL)) DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL)) diff --git a/riscv-tests b/riscv-tests index a4815615..df4967ac 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit a481561500f43c8a022cfc0ba1695914e1df4d57 +Subproject commit df4967acd1a511517977feb63eabd647e6a00701 diff --git a/rocket b/rocket index 347cff51..cceb29c2 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 347cff517b12bf5fe76f410b0108788440aa613e +Subproject commit cceb29c281b6fc8d5aa1ac025d18854db13f10bb From 0ce98a7e0c81e1f120130e40bcc37d59e6c0c596 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 28 Jan 2014 03:52:55 -0800 Subject: [PATCH 15/28] Update riscv-tools --- riscv-tools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-tools b/riscv-tools index d95cb1de..78f57c3f 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit d95cb1dea6b7a339027d751c5e509dbc63ff22f4 +Subproject commit 78f57c3fd83bea98b716b07898d2c21ebc36f064 From 8062888fb992dbba3cb24773af88cc9d2270e0d8 Mon Sep 17 00:00:00 2001 From: Stephen Twigg Date: Tue, 28 Jan 2014 22:14:54 -0800 Subject: [PATCH 16/28] Push hwacha, rocket, chisel to newest versions --- chisel | 2 +- rocket | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/chisel b/chisel index ae1d1de8..8db5030a 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit ae1d1de82188f0a1d79a4e8eb613743942a13eb3 +Subproject commit 8db5030aee11b7205d1d840676d1784aed5dfd8d diff --git a/rocket b/rocket index 9aa03938..674a3ed5 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 9aa03938c05323e292c79b8b5fb4a49e911183d7 +Subproject commit 674a3ed52338493da2b075f4b670e09bcb5a313c From e9d3a650a4614835ca3d0268cea3105ecc554646 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 31 Jan 2014 12:25:19 -0800 Subject: [PATCH 17/28] Speed up C++ compilation --- Makefrag | 2 +- chisel | 2 +- emulator/Makefile | 20 ++++++++++++++------ hardfloat | 2 +- riscv-tests | 2 +- rocket | 2 +- 6 files changed, 19 insertions(+), 11 deletions(-) diff --git a/Makefrag b/Makefrag index 7c92290f..37f4a4fb 100644 --- a/Makefrag +++ b/Makefrag @@ -2,7 +2,7 @@ MODEL := Top CXX := g++ -CXXFLAGS := -O2 +CXXFLAGS := -O1 SBT := java -Xmx2048M -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar diff --git a/chisel b/chisel index 3b1979d8..5c3fc63f 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 3b1979d8a182d9fa8a65ce0523581f353f9f4603 +Subproject commit 5c3fc63f3d58ede49a01689224f2630954a0924f diff --git a/emulator/Makefile b/emulator/Makefile index 674c88a0..c058574a 100644 --- a/emulator/Makefile +++ b/emulator/Makefile @@ -18,22 +18,30 @@ DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL)) CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir emulator/generated-src CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd --ioDebug -generated-src/$(MODEL).cpp: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala +generated-src/$(MODEL).h: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala cd $(base_dir) && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS)" -generated-src-debug/$(MODEL).cpp: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala +generated-src-debug/$(MODEL).h: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala cd $(base_dir) && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS_DEBUG)" -$(MODEL).o: %.o: generated-src/%.cpp +$(MODEL).o: %.o: generated-src/%.h + $(MAKE) -j $(patsubst %.cpp,%.o,$(shell ls generated-src/$(MODEL)-*.cpp)) + $(LD) -r $(patsubst %.cpp,%.o,$(shell ls generated-src/$(MODEL)-*.cpp)) -o $@ + +$(MODEL)-debug.o: %-debug.o: generated-src-debug/%.h + $(MAKE) -j $(patsubst %.cpp,%.o,$(shell ls generated-src-debug/$(MODEL)-*.cpp)) + $(LD) -r $(patsubst %.cpp,%.o,$(shell ls generated-src-debug/$(MODEL)-*.cpp)) -o $@ + +$(wildcard generated-src/*.o): %.o: %.cpp generated-src/$(MODEL).h $(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $< -$(MODEL)-debug.o: %-debug.o: generated-src-debug/%.cpp +$(wildcard generated-src-debug/*.o): %.o: %.cpp generated-src-debug/$(MODEL).h $(CXX) $(CXXFLAGS) -Igenerated-src-debug -c -o $@ $< -$(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h generated-src/$(MODEL).cpp +$(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h generated-src/$(MODEL).h $(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $< -$(addsuffix -debug.o,$(CXXSRCS)): %-debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h generated-src-debug/$(MODEL).cpp +$(addsuffix -debug.o,$(CXXSRCS)): %-debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h generated-src-debug/$(MODEL).h $(CXX) $(CXXFLAGS) -Igenerated-src-debug -c -o $@ $< emulator: $(OBJS) libdramsim.a diff --git a/hardfloat b/hardfloat index ac7ec37a..d1269259 160000 --- a/hardfloat +++ b/hardfloat @@ -1 +1 @@ -Subproject commit ac7ec37adf725caf9291d813e46826a9a7cab22c +Subproject commit d1269259151b25e7a7a1ddc22bf85b92cd732118 diff --git a/riscv-tests b/riscv-tests index df4967ac..7bf1cfb4 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit df4967acd1a511517977feb63eabd647e6a00701 +Subproject commit 7bf1cfb4bc537f8854b298cf4565974dcc2b85b9 diff --git a/rocket b/rocket index cceb29c2..94ebacce 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit cceb29c281b6fc8d5aa1ac025d18854db13f10bb +Subproject commit 94ebacced6aa2bf1e7e0761a0fb0e547d172ee12 From 382fa0ef278ff6121e45ed7602901f11b7b3c373 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 21 Jan 2014 12:37:47 -0800 Subject: [PATCH 18/28] cleanups supporting uncore hierarchy --- riscv-tests | 2 +- rocket | 2 +- src/main/scala/RocketChip.scala | 16 ++--- src/main/scala/fpga.scala | 16 ++--- src/main/scala/network.scala | 117 ++++++++++++++++---------------- uncore | 2 +- 6 files changed, 79 insertions(+), 76 deletions(-) diff --git a/riscv-tests b/riscv-tests index 7bf1cfb4..6ff98375 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit 7bf1cfb4bc537f8854b298cf4565974dcc2b85b9 +Subproject commit 6ff9837501d34c1c8f87ded1fb05fe95987dba2d diff --git a/rocket b/rocket index 94ebacce..2053e9f7 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 94ebacced6aa2bf1e7e0761a0fb0e547d172ee12 +Subproject commit 2053e9f752962e47e9a38ddd540f986a2fe32038 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index deb400f7..0e71cbd3 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -83,7 +83,7 @@ class ReferenceChipBackend extends VerilogBackend transforms += ((c: Module) => collectNodesIntoComp(initializeDFS)) } -class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module +class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module { implicit val (tl, ln, l2) = (conf.tl, conf.tl.ln, conf.l2) val io = new Bundle { @@ -101,10 +101,10 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge //val llc = Module(new DRAMSideLLCNull(NL2_REL_XACTS+NL2_ACQ_XACTS, REFILL_CYCLES)) val mem_serdes = Module(new MemSerdes(htif_width)) - require(clientEndpoints.length == ln.nClients) val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i))) - val net = Module(new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints)) - net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end } + val net = Module(new ReferenceChipCrossbarNetwork) + net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end } + net.io.masters zip (masterEndpoints.map(_.io.client)) map { case (net, end) => net <> end } masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } } val conv = Module(new MemIOUncachedTileLinkIOConverter(2)) @@ -145,7 +145,7 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int) -class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module +class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module { implicit val tl = conf.tl val io = new Bundle { @@ -158,7 +158,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf val mem_backup_en = Bool(INPUT) } val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR)) - val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif)) + val outmemsys = Module(new OuterMemorySystem(htif_width)) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) outmemsys.io.incoherent := incoherentWithHtif htif.io.cpu <> io.htif @@ -246,7 +246,7 @@ class Top extends Module { else new MICoherence } - implicit val ln = LogicalNetworkConfiguration(NTILES+NBANKS+1, log2Up(NTILES)+1, NBANKS, NTILES+1) + implicit val ln = LogicalNetworkConfiguration(log2Up(NTILES)+1, NBANKS, NTILES+1) implicit val tl = TileLinkConfiguration(co, ln, log2Up(NL2_REL_XACTS+NL2_ACQ_XACTS), 2*log2Up(NMSHRS*NTILES+1), MEM_DATA_BITS) implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS) implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64) @@ -261,7 +261,7 @@ class Top extends Module { val resetSigs = Vec.fill(uc.nTiles){Bool()} val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc))) - val uncore = Module(new Uncore(HTIF_WIDTH, tileList)) + val uncore = Module(new Uncore(HTIF_WIDTH)) for (i <- 0 until uc.nTiles) { val hl = uncore.io.htif(i) diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index e491caba..108534f7 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -5,7 +5,7 @@ import Node._ import uncore._ import rocket._ -class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module +class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module { implicit val (tl, ln, l2) = (conf.tl, conf.tl.ln, conf.l2) val io = new Bundle { @@ -15,11 +15,11 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc val mem = new ioMem } - require(clientEndpoints.length == ln.nClients) val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i))) - val net = Module(new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints)) - net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end } + val net = Module(new ReferenceChipCrossbarNetwork) + net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end } + net.io.masters zip (masterEndpoints.map(_.io.client)) map { case (net, end) => net <> end } masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } } val conv = Module(new MemIOUncachedTileLinkIOConverter(2)) @@ -35,7 +35,7 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc conv.io.mem.resp <> Queue(io.mem.resp) } -class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module +class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module { implicit val (tl, ln) = (conf.tl, conf.tl.ln) val io = new Bundle { @@ -46,7 +46,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput } val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR)) - val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif)) + val outmemsys = Module(new FPGAOuterMemorySystem(htif_width)) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) outmemsys.io.incoherent := incoherentWithHtif htif.io.cpu <> io.htif @@ -85,7 +85,7 @@ class FPGATop extends Module { val ntiles = 1 val nbanks = 1 val nmshrs = 2 - implicit val ln = LogicalNetworkConfiguration(ntiles+nbanks+1, log2Up(ntiles)+1, nbanks, ntiles+1) + implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, nbanks, ntiles+1) implicit val tl = TileLinkConfiguration(co, ln, log2Up(1+8), 2*log2Up(nmshrs*ntiles+1), MEM_DATA_BITS) implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8) implicit val uc = UncoreConfiguration(l2, tl, ntiles, nbanks, bankIdLsb = 5, nSCR = 64) @@ -100,7 +100,7 @@ class FPGATop extends Module { val resetSigs = Vec.fill(uc.nTiles){Bool()} val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc))) - val uncore = Module(new FPGAUncore(htif_width, tileList)) + val uncore = Module(new FPGAUncore(htif_width)) for (i <- 0 until uc.nTiles) { val hl = uncore.io.htif(i) diff --git a/src/main/scala/network.scala b/src/main/scala/network.scala index a3a43526..109d4a2b 100644 --- a/src/main/scala/network.scala +++ b/src/main/scala/network.scala @@ -3,25 +3,26 @@ package referencechip import Chisel._ import uncore._ import scala.reflect._ +import scala.reflect.runtime.universe._ object TileLinkHeaderAppender { - def apply[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasTileLinkData](in: ClientSourcedDataIO[LogicalNetworkIO[T],LogicalNetworkIO[U]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = { + def apply[T <: ClientSourcedMessage with HasPhysicalAddress, U <: ClientSourcedMessage with HasTileLinkData](in: PairedDataIO[LogicalNetworkIO[T],LogicalNetworkIO[U]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = { val shim = Module(new TileLinkHeaderAppender(in.meta.bits.payload, in.data.bits.payload, clientId, nBanks, addrConvert)) shim.io.in <> in shim.io.out } - def apply[T <: SourcedMessage with HasPhysicalAddress](in: ClientSourcedFIFOIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = { + def apply[T <: ClientSourcedMessage with HasPhysicalAddress](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) = { val shim = Module(new TileLinkHeaderAppender(in.bits.payload.clone, new AcquireData, clientId, nBanks, addrConvert)) shim.io.in.meta <> in shim.io.out.meta } } -class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasTileLinkData](mType: T, dType: U, clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) extends Module { +class TileLinkHeaderAppender[T <: ClientSourcedMessage with HasPhysicalAddress, U <: ClientSourcedMessage with HasTileLinkData](mType: T, dType: U, clientId: Int, nBanks: Int, addrConvert: Bits => UInt)(implicit conf: TileLinkConfiguration) extends Module { implicit val ln = conf.ln val io = new Bundle { - val in = new ClientSourcedDataIO(new LogicalNetworkIO(mType), new LogicalNetworkIO(dType)).flip - val out = new ClientSourcedDataIO(new LogicalNetworkIO(mType), new LogicalNetworkIO(dType)) + val in = new PairedDataIO(new LogicalNetworkIO(mType), new LogicalNetworkIO(dType)).flip + val out = new PairedDataIO(new LogicalNetworkIO(mType), new LogicalNetworkIO(dType)) } val meta_q = Queue(io.in.meta) @@ -93,11 +94,21 @@ class MemIOUncachedTileLinkIOConverter(qDepth: Int)(implicit conf: TileLinkConfi io.mem.req_data <> mem_data_q.io.deq } -class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit conf: UncoreConfiguration) extends LogicalNetwork[TileLinkIO](endpoints)(conf.tl.ln) { +class ReferenceChipCrossbarNetwork(implicit conf: UncoreConfiguration) extends LogicalNetwork[TileLinkIO]()(conf.tl.ln) { implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co) - val io = Vec(endpoints.map(_ match { case t:ClientCoherenceAgent => {(new TileLinkIO).flip}; case h:MasterCoherenceAgent => {new TileLinkIO}})) + val io = new Bundle { + val clients = Vec.fill(ln.nClients){(new TileLinkIO).flip} + val masters = Vec.fill(ln.nMasters){new TileLinkIO} + } implicit val pconf = new PhysicalNetworkConfiguration(ln.nEndpoints, ln.idBits) // Same config for all networks + // Actually instantiate the particular networks required for TileLink + val acqNet = Module(new PairedCrossbar(new Acquire, new AcquireData, REFILL_CYCLES, (acq: PhysicalNetworkIO[Acquire]) => co.messageHasData(acq.payload))) + val relNet = Module(new PairedCrossbar(new Release, new ReleaseData, REFILL_CYCLES, (rel: PhysicalNetworkIO[Release]) => co.messageHasData(rel.payload))) + val probeNet = Module(new BasicCrossbar(new Probe)) + val grantNet = Module(new BasicCrossbar(new Grant)) + val ackNet = Module(new BasicCrossbar(new GrantAck)) + // Aliases for the various network IO bundle types type FBCIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]] type FLNIO[T <: Data] = DecoupledIO[LogicalNetworkIO[T]] @@ -163,61 +174,53 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit phys_in.valid := Bool(false) } - // Use reflection to determine whether a particular endpoint should be - // hooked up as an [input/output] for a FIFO nework that is transmiitting - // [client/master]-sourced messages. - def doFIFOHookup[S <: CoherenceAgentRole: ClassTag, T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], inShim: ToCrossbar[T], outShim: FromCrossbar[T]) = { - // Is end's type a subtype of S, the agent type associated with inputs? - if(classTag[S].runtimeClass.isInstance(end)) - doFIFOInputHookup(phys_in, phys_out, log_io, inShim) - else - doFIFOOutputHookup(phys_in, phys_out, log_io, outShim) + def doFIFOHookup[T <: Data](isEndpointSourceOfMessage: Boolean, physIn: FBCIO[T], physOut: FBCIO[T], logIO: FLNIO[T], inShim: ToCrossbar[T], outShim: FromCrossbar[T]) = { + if(isEndpointSourceOfMessage) doFIFOInputHookup(physIn, physOut, logIO, inShim) + else doFIFOOutputHookup(physIn, physOut, logIO, outShim) } - - def doClientSourcedFIFOHookup[T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T]) = - doFIFOHookup[ClientCoherenceAgent, T](end, phys_in, phys_out, log_io, ClientToCrossbarShim, CrossbarToMasterShim) - - def doMasterSourcedFIFOHookup[T <: Data](end: CoherenceAgentRole, phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T]) = - doFIFOHookup[MasterCoherenceAgent, T](end, phys_in, phys_out, log_io, MasterToCrossbarShim, CrossbarToClientShim) - // Use reflection to determine whether a particular endpoint should be - // hooked up as an [input/output] for a Paired nework that is transmiitting - // [client/master]-sourced messages. - def doPairedDataHookup[S <: CoherenceAgentRole : ClassTag, T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R], inShim: ToCrossbar[T], outShim: FromCrossbar[T], inShimD: ToCrossbar[R], outShimD: FromCrossbar[R]) = { - // Is end's type a subtype of S, the agent type associated with inputs? - if(classTag[S].runtimeClass.isInstance(end)) { - doFIFOInputHookup[T](phys_in.meta, phys_out.meta, log_io.meta, inShim) - doFIFOInputHookup[R](phys_in.data, phys_out.data, log_io.data, inShimD) - } else { - doFIFOOutputHookup[T](phys_in.meta, phys_out.meta, log_io.meta, outShim) - doFIFOOutputHookup[R](phys_in.data, phys_out.data, log_io.data, outShimD) + //Hookup all instances of a particular subbundle of + def doFIFOHookups[T <: Data: TypeTag](physIO: BasicCrossbarIO[T], getLogIO: TileLinkIO => FLNIO[T]) = { + typeTag[T].tpe match{ + case t if t <:< typeTag[ClientSourcedMessage].tpe => { + io.masters.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id), physIO.out(id), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) } + io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) } + } + case t if t <:< typeTag[MasterSourcedMessage].tpe => { + io.masters.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id), physIO.out(id), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) } + io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) } + } + case _ => require(false, "Unknown message sourcing.") } } - def doClientSourcedPairedHookup[T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R]) = - doPairedDataHookup[ClientCoherenceAgent, T, R](end, phys_in, phys_out, log_io, ClientToCrossbarShim, CrossbarToMasterShim, ClientToCrossbarShim, CrossbarToMasterShim) + def doPairedDataHookup[T <: Data, R <: Data](isEndpointSourceOfMessage: Boolean, physIn: PBCIO[T,R], physOut: PBCIO[T,R], logIO: PLNIO[T,R], inShim: ToCrossbar[T], outShim: FromCrossbar[T], inShimD: ToCrossbar[R], outShimD: FromCrossbar[R]) = { + if(isEndpointSourceOfMessage) { + doFIFOInputHookup[T](physIn.meta, physOut.meta, logIO.meta, inShim) + doFIFOInputHookup[R](physIn.data, physOut.data, logIO.data, inShimD) + } else { + doFIFOOutputHookup[T](physIn.meta, physOut.meta, logIO.meta, outShim) + doFIFOOutputHookup[R](physIn.data, physOut.data, logIO.data, outShimD) + } + } - def doMasterSourcedPairedHookup[T <: Data, R <: Data](end: CoherenceAgentRole, phys_in: PBCIO[T,R], phys_out: PBCIO[T,R], log_io: PLNIO[T,R]) = - doPairedDataHookup[MasterCoherenceAgent, T, R](end, phys_in, phys_out, log_io, MasterToCrossbarShim, CrossbarToClientShim, MasterToCrossbarShim, CrossbarToClientShim) + def doPairedDataHookups[T <: Data: TypeTag, R <: Data](physIO: PairedCrossbarIO[T,R], getLogIO: TileLinkIO => PLNIO[T,R]) = { + typeTag[T].tpe match{ + case t if t <:< typeTag[ClientSourcedMessage].tpe => { + io.masters.zipWithIndex.map{ case (i, id) => doPairedDataHookup[T,R](false, physIO.in(id), physIO.out(id), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim, ClientToCrossbarShim, CrossbarToMasterShim) } + io.clients.zipWithIndex.map{ case (i, id) => doPairedDataHookup[T,R](true, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim, ClientToCrossbarShim, CrossbarToMasterShim) } + } + case t if t <:< typeTag[MasterSourcedMessage].tpe => { + io.masters.zipWithIndex.map{ case (i, id) => doPairedDataHookup[T,R](true, physIO.in(id), physIO.out(id), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim, MasterToCrossbarShim, CrossbarToClientShim) } + io.clients.zipWithIndex.map{ case (i, id) => doPairedDataHookup[T,R](false, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim, MasterToCrossbarShim, CrossbarToClientShim) } + } + case _ => require(false, "Unknown message sourcing.") + } + } - - // Actually instantiate the particular networks required for TileLink - def acqHasData(acq: PhysicalNetworkIO[Acquire]) = co.messageHasData(acq.payload) - val acq_net = Module(new PairedCrossbar(new Acquire, new AcquireData, REFILL_CYCLES, acqHasData _)) - endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, acq_net.io.in(id), acq_net.io.out(id), io.acquire) } - - def relHasData(rel: PhysicalNetworkIO[Release]) = co.messageHasData(rel.payload) - val rel_net = Module(new PairedCrossbar(new Release, new ReleaseData, REFILL_CYCLES, relHasData _)) - endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, rel_net.io.in(id), rel_net.io.out(id), io.release) } - - val probe_net = Module(new BasicCrossbar(new Probe)) - endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doMasterSourcedFIFOHookup(end, probe_net.io.in(id), probe_net.io.out(id), io.probe) } - - val grant_net = Module(new BasicCrossbar(new Grant)) - endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doMasterSourcedFIFOHookup(end, grant_net.io.in(id), grant_net.io.out(id), io.grant) } - - val ack_net = Module(new BasicCrossbar(new GrantAck)) - endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedFIFOHookup(end, ack_net.io.in(id), ack_net.io.out(id), io.grant_ack) } - - val physicalNetworks = List(acq_net, rel_net, probe_net, grant_net, ack_net) + doPairedDataHookups(acqNet.io, (tl: TileLinkIO) => tl.acquire) + doPairedDataHookups(relNet.io, (tl: TileLinkIO) => tl.release) + doFIFOHookups(probeNet.io, (tl: TileLinkIO) => tl.probe) + doFIFOHookups(grantNet.io, (tl: TileLinkIO) => tl.grant) + doFIFOHookups(ackNet.io, (tl: TileLinkIO) => tl.grant_ack) } diff --git a/uncore b/uncore index a5826575..f2a0b435 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit a58265755fcb90aebe5377cb9b7343732fd14b9a +Subproject commit f2a0b435fd98f323b97c423c9cbcd0cb3d03a406 From fc52840ce2dffc3a7f9b996b7b34cd1649eae7e4 Mon Sep 17 00:00:00 2001 From: Christopher Celio Date: Fri, 31 Jan 2014 16:52:59 -0800 Subject: [PATCH 19/28] move timeout in Makefile to a variable --- emulator/Makefile | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/emulator/Makefile b/emulator/Makefile index c058574a..e42184ca 100644 --- a/emulator/Makefile +++ b/emulator/Makefile @@ -60,6 +60,8 @@ test: # Run assembly tests and benchmarks #-------------------------------------------------------------------- +MAX_CYCLES=30000000 + %.hex: $(MAKE) -C $(dir $@) $(notdir $@) @@ -82,15 +84,15 @@ output: mkdir -p $@ output/%.run: output/%.hex emulator - ./emulator +dramsim +max-cycles=30000000 +loadmem=$< none 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ] + ./emulator +dramsim +max-cycles=$(MAX_CYCLES) +loadmem=$< none 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ] output/%.out: output/%.hex emulator - ./emulator +dramsim +max-cycles=30000000 +verbose +coremap-random +loadmem=$< none $(disasm) $@ && [ $$PIPESTATUS -eq 0 ] + ./emulator +dramsim +max-cycles=$(MAX_CYCLES) +verbose +coremap-random +loadmem=$< none $(disasm) $@ && [ $$PIPESTATUS -eq 0 ] output/%.vpd: output/%.hex emulator-debug rm -rf $@.vcd && mkfifo $@.vcd vcd2vpd $@.vcd $@ > /dev/null & - ./emulator-debug +dramsim +max-cycles=30000000 +verbose -v$@.vcd +coremap-random +loadmem=$< none $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ] + ./emulator-debug +dramsim +max-cycles=$(MAX_CYCLES) +verbose -v$@.vcd +coremap-random +loadmem=$< none $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ] run-asm-tests: $(addprefix output/, $(addsuffix .out, $(asm_p_tests) $(asm_v_tests))) @echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo; From 107aa0defae9e2f4132f75e5fc0bd33163cdce1b Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Wed, 5 Feb 2014 03:28:22 -0800 Subject: [PATCH 20/28] recode expander/bank/lfu --- chisel | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chisel b/chisel index b88b521f..13f7e137 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit b88b521f07476f4d113bd970f8cf58e9b8233881 +Subproject commit 13f7e13730657c370ab0a91f5bf046661f4a8359 From dbeadba2dcd2dada17574152d7746893bec575c7 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Wed, 5 Feb 2014 03:28:33 -0800 Subject: [PATCH 21/28] add vfmvv --- Makefrag | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefrag b/Makefrag index 3e79260a..a398bae5 100644 --- a/Makefrag +++ b/Makefrag @@ -214,6 +214,7 @@ vecasm_p_tests = \ rv64uv-p-utidx \ rv64uv-p-vmsv \ rv64uv-p-vmvv \ + rv64uv-p-vfmvv \ rv64uv-p-vsetcfg \ rv64uv-p-vsetcfgi \ rv64uv-p-vsetvl \ From 5128298e8aed8a835f3c8b7374b659f5e226a833 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Wed, 5 Feb 2014 03:29:23 -0800 Subject: [PATCH 22/28] allow chisel to elaborate Modules outside of the ReferenceChip package --- project/build.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/project/build.scala b/project/build.scala index 3076ba9e..a6f98650 100644 --- a/project/build.scala +++ b/project/build.scala @@ -47,7 +47,7 @@ object BuildSettings extends Build { val chiselMainObject = chiselMainClass.getDeclaredFields.head.get(null) val chiselMain = chiselMainClass.getMethod("run", classOf[Array[String]], classOf[Function0[_]]) val chiselArgs = args.drop(numArgs) - val component = classLoader.loadClass(packageName+"."+componentName) + val component = classLoader.loadClass((if (!componentName.contains('.')) packageName+"." else "")+componentName) val generator = () => component.newInstance() chiselMain.invoke(chiselMainObject, Array(chiselArgs.toArray, generator):_*) } From ac8ff4b7e8d521577f7c4e8b7fb8d473baac5c8c Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Thu, 6 Feb 2014 00:12:41 -0800 Subject: [PATCH 23/28] getting vector exceptions to work --- riscv-tests | 2 +- rocket | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv-tests b/riscv-tests index f6d8b485..6fdd12c1 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit f6d8b4850e6c10804059fe94489cdf9455e208af +Subproject commit 6fdd12c130d0c0c13934364a4dfe12d8dcf28e27 diff --git a/rocket b/rocket index d6312342..3a723ddf 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit d631234253aefeb86a8e06ec77ab08b8b1affd53 +Subproject commit 3a723ddfeee470cb3a8837073f623716b63553d5 From e20de64b8c4f023db5cfc88a3d2847ae8fdbe656 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Thu, 6 Feb 2014 00:30:31 -0800 Subject: [PATCH 24/28] rocket sync up --- rocket | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket b/rocket index 3a723ddf..42f215b3 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 3a723ddfeee470cb3a8837073f623716b63553d5 +Subproject commit 42f215b37a89037be2065ada25d078409f81bcdb From 11e69a73cdcf270a163060d1a4e04b112492d15d Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 6 Feb 2014 03:08:33 -0800 Subject: [PATCH 25/28] Fix tests when !hwacha; disable hwacha by default --- chisel | 2 +- hardfloat | 2 +- riscv-tests | 2 +- riscv-tools | 2 +- rocket | 2 +- src/main/scala/RocketChip.scala | 4 +--- 6 files changed, 6 insertions(+), 8 deletions(-) diff --git a/chisel b/chisel index 13f7e137..213d7d6f 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 13f7e13730657c370ab0a91f5bf046661f4a8359 +Subproject commit 213d7d6fc5a5d35c3665490b955a64aacf3a354d diff --git a/hardfloat b/hardfloat index ac7ec37a..d1269259 160000 --- a/hardfloat +++ b/hardfloat @@ -1 +1 @@ -Subproject commit ac7ec37adf725caf9291d813e46826a9a7cab22c +Subproject commit d1269259151b25e7a7a1ddc22bf85b92cd732118 diff --git a/riscv-tests b/riscv-tests index 6fdd12c1..e5d9d1af 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit 6fdd12c130d0c0c13934364a4dfe12d8dcf28e27 +Subproject commit e5d9d1af2e54d50ff2756a8a868c6e7436739311 diff --git a/riscv-tools b/riscv-tools index 76441991..3338089d 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 76441991a8669da66b0d4a716fdbfdf846888684 +Subproject commit 3338089dbd9da62784544b03630aa8df18bd89de diff --git a/rocket b/rocket index 42f215b3..08cd7342 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 42f215b37a89037be2065ada25d078409f81bcdb +Subproject commit 08cd734296ff1bf11695a0adc80077bad4d0b57d diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 3359ca21..8fe62eea 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -257,9 +257,7 @@ class Top extends Module { val vic = ICacheConfig(128, 1) val hc = hwacha.HwachaConfiguration(vic, 8, 256, ndtlb = 8, nptlb = 2) val rc = RocketConfiguration(tl, ic, dc, - fpu = HAS_FPU, - rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c)) - ) + fpu = HAS_FPU) val io = new VLSITopIO(HTIF_WIDTH) From 79486c5802650f088fa17fb14711ef42ffedd08e Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Thu, 6 Feb 2014 11:25:45 -0800 Subject: [PATCH 26/28] push tools,tests --- riscv-tests | 2 +- riscv-tools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv-tests b/riscv-tests index e5d9d1af..c14db8a3 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit e5d9d1af2e54d50ff2756a8a868c6e7436739311 +Subproject commit c14db8a34bb427406b5900de0bfa770ec0978623 diff --git a/riscv-tools b/riscv-tools index 3338089d..fd1f3f49 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 3338089dbd9da62784544b03630aa8df18bd89de +Subproject commit fd1f3f49f9bd332dae15e22ad478ccfe0078406f From cda46b3ce1bd826b65889e22a06ffebcd350c8d4 Mon Sep 17 00:00:00 2001 From: Scott Beamer Date: Thu, 6 Feb 2014 16:20:48 -0800 Subject: [PATCH 27/28] use --recursive to populate all submodules. with current instructions you can't run tests because riscv-tests/env isn't pulled in --- README | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/README b/README index 1ae6d470..2e325570 100644 --- a/README +++ b/README @@ -2,10 +2,7 @@ Quick and dirty instructions: CHECKOUT THE CODE: - git submodule update --init - - cd riscv-tools - git submodule update --init + git submodule update --init --recursive BUILDING THE TOOLCHAIN: From 0ebb115a3c8c0a21584d72f2b43d6fdf9bd03045 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 10 Feb 2014 19:05:14 -0800 Subject: [PATCH 28/28] Revert to old AUIPC definition --- chisel | 2 +- riscv-tests | 2 +- riscv-tools | 2 +- rocket | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/chisel b/chisel index 213d7d6f..f6bee8a4 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 213d7d6fc5a5d35c3665490b955a64aacf3a354d +Subproject commit f6bee8a4d930b613262addac8af91ed57ab1c329 diff --git a/riscv-tests b/riscv-tests index c14db8a3..c50db79a 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit c14db8a34bb427406b5900de0bfa770ec0978623 +Subproject commit c50db79a8e549d7dd2112ff22d48be5e4b501fea diff --git a/riscv-tools b/riscv-tools index fd1f3f49..9a2d419b 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit fd1f3f49f9bd332dae15e22ad478ccfe0078406f +Subproject commit 9a2d419bc39ca52d1866ac3ec5ed16c7d71d157c diff --git a/rocket b/rocket index 08cd7342..3fd05361 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 08cd734296ff1bf11695a0adc80077bad4d0b57d +Subproject commit 3fd053615ec23f89dfc53b5cc2713343b1800ac7