riscv/rocket-chip
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WIP on PMP

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Andrew Waterman committed 2017-03-24 16:39:52 -07:00
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commit aace526857
7 files changed
+150 -6
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src/main/scala/tile/Core.scala
+1 -1
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@@ -43,7 +43,7 @@ trait HasCoreParameters extends HasTileParameters {
val coreInstBits = coreParams.instBits
val coreInstBytes = coreInstBits/8
val coreDataBits = xLen
val coreDataBits = xLen max fLen
val coreDataBytes = coreDataBits/8
val coreDCacheReqTagBits = 6