riscv/rocket-chip
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WIP on PMP

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Andrew Waterman
2017-03-15 01:18:39 -07:00
parent b1b405404d
commit aace526857
7 changed files with 150 additions and 6 deletions
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src/main/scala/tile/Core.scala
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@ -43,7 +43,7 @@ trait HasCoreParameters extends HasTileParameters {
val coreInstBits = coreParams.instBits
val coreInstBytes = coreInstBits/8
val coreDataBits = xLen
val coreDataBits = xLen max fLen
val coreDataBytes = coreDataBits/8
val coreDCacheReqTagBits = 6