riscv/rocket-chip
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WIP on PMP

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This commit is contained in:
Andrew Waterman
2017-03-15 01:18:39 -07:00
parent b1b405404d
commit aace526857
7 changed files with 150 additions and 6 deletions
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9
src/main/scala/rocket/PTW.scala
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@ -26,17 +26,21 @@ class PTWResp(implicit p: Parameters) extends CoreBundle()(p) {
val level = UInt(width = log2Ceil(pgLevels))
}
class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) {
class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p)
with HasRocketCoreParameters {
val req = Decoupled(new PTWReq)
val resp = Valid(new PTWResp).flip
val ptbr = new PTBR().asInput
val status = new MStatus().asInput
val pmp = Vec(nPMPs, new PMP).asInput
}
class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) {
class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p)
with HasRocketCoreParameters {
val ptbr = new PTBR().asInput
val invalidate = Bool(INPUT)
val status = new MStatus().asInput
val pmp = Vec(nPMPs, new PMP).asInput
}
class PTE(implicit p: Parameters) extends CoreBundle()(p) {
@ -138,6 +142,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
io.requestor(i).resp.bits.pte.ppn := pte_addr >> pgIdxBits
io.requestor(i).ptbr := io.dpath.ptbr
io.requestor(i).status := io.dpath.status
io.requestor(i).pmp := io.dpath.pmp
}
// control state machine