riscv/rocket-chip
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Add PLIC

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This commit is contained in:
Andrew Waterman
2016-05-10 00:27:31 -07:00
parent df479d7935
commit aac89ca1f0
5 changed files with 60 additions and 12 deletions
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24
src/main/scala/Configs.scala
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@ -27,10 +27,11 @@ class DefaultConfig extends Config (
lazy val internalIOAddrMap: AddrMap = {
val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
entries += AddrMapEntry("debug", MemSize(1<<12, 1<<12, MemAttr(0)))
entries += AddrMapEntry("bootrom", MemSize(1<<13, 1<<12, MemAttr(AddrMapProt.RX)))
entries += AddrMapEntry("bootrom", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RX)))
entries += AddrMapEntry("rtc", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW)))
for (i <- 0 until site(NTiles))
entries += AddrMapEntry(s"prci$i", MemSize(1<<12, 1<<12, MemAttr(AddrMapProt.RW)))
entries += AddrMapEntry("plic", MemSize(1<<22, 1<<22, MemAttr(AddrMapProt.RW)))
new AddrMap(entries)
}
lazy val (globalAddrMap, globalAddrHashMap) = {
@ -54,12 +55,19 @@ class DefaultConfig extends Config (
}
def makeConfigString() = {
val addrMap = globalAddrHashMap
val plicAddr = addrMap(s"io:int:plic").start
val plicInfo = site(PLICKey)
val xLen = site(XLen)
val res = new StringBuilder
res append "platform {\n"
res append " vendor ucb;\n"
res append " arch rocket;\n"
res append "};\n"
res append "plic {\n"
res append s" priority 0x${plicAddr.toString(16)};\n"
res append s" pending 0x${(plicAddr + plicInfo.pendingBase).toString(16)};\n"
res append s" ndevs ${plicInfo.nDevices};\n"
res append "};\n"
res append "rtc {\n"
res append s" addr 0x${addrMap("io:int:rtc").start.toString(16)};\n"
res append "};\n"
@ -79,6 +87,18 @@ class DefaultConfig extends Config (
res append s" isa $isa;\n"
res append s" timecmp 0x${timecmpAddr.toString(16)};\n"
res append s" ipi 0x${prciAddr.toString(16)};\n"
res append s" plic {\n"
res append s" m {\n"
res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'M')).toString(16)};\n"
res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'M')).toString(16)};\n"
res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'M')).toString(16)};\n"
res append s" };\n"
res append s" s {\n"
res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'S')).toString(16)};\n"
res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'S')).toString(16)};\n"
res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'S')).toString(16)};\n"
res append s" };\n"
res append s" };\n"
res append " };\n"
res append " };\n"
}
@ -194,6 +214,8 @@ class DefaultConfig extends Config (
else TestGeneration.addSuites(env.map(rv64ufNoDiv))
true
}
case NExtInterrupts => 2
case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), site(NExtInterrupts))
case FDivSqrt => true
case SFMALatency => 2
case DFMALatency => 3