From aabd17d935e72416591a60cf9a8751ceeff20d43 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sat, 29 Oct 2016 03:30:49 -0700 Subject: [PATCH] rocketchip: must create bundles within Module scope 1. Bundles be created after base class Module constructor runs 2. Bundles must be created before Module(...) runs Solution: pass a bundle constructor to the cake base class Require the constructor to take a parameter so people don't use it by accident; they should get a type error. Consistently name all the cake arguments with an _io, _coreplex, _outer, so that they don't shadow the base class variables you should be using. --- src/main/scala/coreplex/BaseCoreplex.scala | 17 ++++++++++------- src/main/scala/coreplex/Coreplex.scala | 12 ++++++------ src/main/scala/groundtest/Coreplex.scala | 6 +++--- src/main/scala/rocketchip/BaseTop.scala | 22 +++++++++++++--------- src/main/scala/rocketchip/ExampleTop.scala | 16 ++++++++-------- 5 files changed, 40 insertions(+), 33 deletions(-) diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index 78f3f997..3392b020 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -44,9 +44,12 @@ trait HasCoreplexParameters { case class CoreplexParameters(implicit val p: Parameters) extends HasCoreplexParameters abstract class BareCoreplex(implicit val p: Parameters) extends LazyModule -abstract class BareCoreplexBundle[+L <: BareCoreplex](val outer: L) extends Bundle -abstract class BareCoreplexModule[+B <: BareCoreplexBundle[BareCoreplex]](val io: B) extends LazyModuleImp(io.outer) { - val outer = io.outer.asInstanceOf[io.outer.type] +abstract class BareCoreplexBundle[+L <: BareCoreplex](_outer: L) extends Bundle { + val outer = _outer +} +abstract class BareCoreplexModule[+L <: BareCoreplex, +B <: BareCoreplexBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) { + val outer = _outer + val io = _io () } trait CoreplexNetwork extends HasCoreplexParameters { @@ -86,7 +89,7 @@ trait CoreplexNetworkBundle extends HasCoreplexParameters { } trait CoreplexNetworkModule extends HasCoreplexParameters { - this: BareCoreplexModule[BareCoreplexBundle[BareCoreplex]] => + this: BareCoreplexModule[BareCoreplex, BareCoreplexBundle[BareCoreplex]] => implicit val p = outer.p } @@ -228,13 +231,13 @@ trait CoreplexRISCVModule { class BaseCoreplex(implicit p: Parameters) extends BareCoreplex with CoreplexNetwork with CoreplexRISCV { - override lazy val module = new BaseCoreplexModule(new BaseCoreplexBundle(this)) + override lazy val module = new BaseCoreplexModule(this, () => new BaseCoreplexBundle(this)) } -class BaseCoreplexBundle[+L <: BaseCoreplex](outer: L) extends BareCoreplexBundle(outer) +class BaseCoreplexBundle[+L <: BaseCoreplex](_outer: L) extends BareCoreplexBundle(_outer) with CoreplexNetworkBundle with CoreplexRISCVBundle -class BaseCoreplexModule[+B <: BaseCoreplexBundle[BaseCoreplex]](io: B) extends BareCoreplexModule(io) +class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle[L]](_outer: L, _io: () => B) extends BareCoreplexModule(_outer, _io) with CoreplexNetworkModule with CoreplexRISCVModule diff --git a/src/main/scala/coreplex/Coreplex.scala b/src/main/scala/coreplex/Coreplex.scala index d5bd9892..4a9e279a 100644 --- a/src/main/scala/coreplex/Coreplex.scala +++ b/src/main/scala/coreplex/Coreplex.scala @@ -34,12 +34,12 @@ trait DirectConnectionModule { class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex with DirectConnection { - override lazy val module = new DefaultCoreplexModule(new DefaultCoreplexBundle(this)) + override lazy val module = new DefaultCoreplexModule(this, () => new DefaultCoreplexBundle(this)) } -class DefaultCoreplexBundle[+L <: DefaultCoreplex](outer: L) extends BaseCoreplexBundle(outer) +class DefaultCoreplexBundle[+L <: DefaultCoreplex](_outer: L) extends BaseCoreplexBundle(_outer) -class DefaultCoreplexModule[+B <: DefaultCoreplexBundle[DefaultCoreplex]](io: B) extends BaseCoreplexModule(io) +class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io) with DirectConnectionModule ///// @@ -103,11 +103,11 @@ trait AsyncConnectionModule { class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex with AsyncConnection { - override lazy val module = new MultiClockCoreplexModule(new MultiClockCoreplexBundle(this)) + override lazy val module = new MultiClockCoreplexModule(this, () => new MultiClockCoreplexBundle(this)) } -class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](outer: L) extends BaseCoreplexBundle(outer) +class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](_outer: L) extends BaseCoreplexBundle(_outer) with AsyncConnectionBundle -class MultiClockCoreplexModule[+B <: MultiClockCoreplexBundle[MultiClockCoreplex]](io: B) extends BaseCoreplexModule(io) +class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io) with AsyncConnectionModule diff --git a/src/main/scala/groundtest/Coreplex.scala b/src/main/scala/groundtest/Coreplex.scala index 04cb2650..738b02f8 100644 --- a/src/main/scala/groundtest/Coreplex.scala +++ b/src/main/scala/groundtest/Coreplex.scala @@ -6,12 +6,12 @@ import coreplex._ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex with DirectConnection { - override lazy val module = new GroundTestCoreplexModule(new GroundTestCoreplexBundle(this)) + override lazy val module = new GroundTestCoreplexModule(this, () => new GroundTestCoreplexBundle(this)) } -class GroundTestCoreplexBundle[+L <: GroundTestCoreplex](outer: L) extends BaseCoreplexBundle(outer) +class GroundTestCoreplexBundle[+L <: GroundTestCoreplex](_outer: L) extends BaseCoreplexBundle(_outer) -class GroundTestCoreplexModule[+B <: GroundTestCoreplexBundle[GroundTestCoreplex]](io: B) extends BaseCoreplexModule(io) +class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io) with DirectConnectionModule { io.success := tiles.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_) } diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala index a66276bc..d17e95e4 100644 --- a/src/main/scala/rocketchip/BaseTop.scala +++ b/src/main/scala/rocketchip/BaseTop.scala @@ -19,11 +19,11 @@ case object NCoreplexExtClients extends Field[Int] /** Enable or disable monitoring of Diplomatic buses */ case object TLEmitMonitors extends Field[Bool] -abstract class BareTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit val q: Parameters) extends LazyModule { +abstract class BareTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit val q: Parameters) extends LazyModule { // Fill in the TL1 legacy parameters; remove these once rocket/groundtest/unittest are TL2 val pBusMasters = new RangeManager lazy val legacyAddrMap = GenerateGlobalAddrMap(q, coreplex.l1tol2.node.edgesIn(0).manager.managers) - val coreplex : C = LazyModule(buildCoreplex(q.alterPartial { + val coreplex : C = LazyModule(_coreplex(q.alterPartial { case NCoreplexExtClients => pBusMasters.sum case GlobalAddrMap => legacyAddrMap })) @@ -31,9 +31,13 @@ abstract class BareTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(impli TopModule.contents = Some(this) } -abstract class BareTopBundle[+L <: BareTop[BaseCoreplex]](val outer: L) extends Bundle -abstract class BareTopModule[+B <: BareTopBundle[BareTop[BaseCoreplex]]](val io: B) extends LazyModuleImp(io.outer) { - val outer = io.outer.asInstanceOf[io.outer.type] +abstract class BareTopBundle[+L <: BareTop[BaseCoreplex]](_outer: L) extends Bundle { + val outer = _outer +} + +abstract class BareTopModule[+L <: BareTop[BaseCoreplex], +B <: BareTopBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) { + val outer = _outer + val io = _io () } /** Base Top with no Periphery */ @@ -76,15 +80,15 @@ trait TopNetworkModule extends HasPeripheryParameters { } /** Base Top with no Periphery */ -class BaseTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit p: Parameters) extends BareTop(buildCoreplex) +class BaseTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BareTop(_coreplex) with TopNetwork { - override lazy val module = new BaseTopModule(new BaseTopBundle(this)) + override lazy val module = new BaseTopModule(this, () => new BaseTopBundle(this)) } -class BaseTopBundle[+L <: BaseTop[BaseCoreplex]](outer: L) extends BareTopBundle(outer) +class BaseTopBundle[+L <: BaseTop[BaseCoreplex]](_outer: L) extends BareTopBundle(_outer) with TopNetworkBundle -class BaseTopModule[+B <: BaseTopBundle[BaseTop[BaseCoreplex]]](io: B) extends BareTopModule(io) +class BaseTopModule[+L <: BaseTop[BaseCoreplex], +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io) with TopNetworkModule trait DirectConnection { diff --git a/src/main/scala/rocketchip/ExampleTop.scala b/src/main/scala/rocketchip/ExampleTop.scala index 847781bf..5b17b242 100644 --- a/src/main/scala/rocketchip/ExampleTop.scala +++ b/src/main/scala/rocketchip/ExampleTop.scala @@ -9,7 +9,7 @@ import coreplex._ import rocketchip._ /** Example Top with Periphery */ -class ExampleTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(buildCoreplex) +class ExampleTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(_coreplex) with PeripheryBootROM with PeripheryDebug with PeripheryExtInterrupts @@ -17,10 +17,10 @@ class ExampleTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit p: with PeripheryMasterAXI4MMIO with PeripherySlave with DirectConnection { - override lazy val module = new ExampleTopModule(new ExampleTopBundle(this)) + override lazy val module = new ExampleTopModule(this, () => new ExampleTopBundle(this)) } -class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](outer: L) extends BaseTopBundle(outer) +class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](_outer: L) extends BaseTopBundle(_outer) with PeripheryBootROMBundle with PeripheryDebugBundle with PeripheryExtInterruptsBundle @@ -28,7 +28,7 @@ class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](outer: L) extends BaseTop with PeripheryMasterAXI4MMIOBundle with PeripherySlaveBundle -class ExampleTopModule[+B <: ExampleTopBundle[ExampleTop[BaseCoreplex]]](io: B) extends BaseTopModule(io) +class ExampleTopModule[+L <: ExampleTop[BaseCoreplex], +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io) with PeripheryBootROMModule with PeripheryDebugModule with PeripheryExtInterruptsModule @@ -39,13 +39,13 @@ class ExampleTopModule[+B <: ExampleTopBundle[ExampleTop[BaseCoreplex]]](io: B) with DirectConnectionModule /** Example Top with TestRAM */ -class ExampleTopWithTestRAM[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(buildCoreplex) +class ExampleTopWithTestRAM[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(_coreplex) with PeripheryTestRAM { - override lazy val module = new ExampleTopWithTestRAMModule(new ExampleTopWithTestRAMBundle(this)) + override lazy val module = new ExampleTopWithTestRAMModule(this, () => new ExampleTopWithTestRAMBundle(this)) } -class ExampleTopWithTestRAMBundle[+L <: ExampleTopWithTestRAM[BaseCoreplex]](outer: L) extends ExampleTopBundle(outer) +class ExampleTopWithTestRAMBundle[+L <: ExampleTopWithTestRAM[BaseCoreplex]](_outer: L) extends ExampleTopBundle(_outer) with PeripheryTestRAMBundle -class ExampleTopWithTestRAMModule[+B <: ExampleTopWithTestRAMBundle[ExampleTopWithTestRAM[BaseCoreplex]]](io: B) extends ExampleTopModule(io) +class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM[BaseCoreplex], +B <: ExampleTopWithTestRAMBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io) with PeripheryTestRAMModule