riscv/rocket-chip
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Add an intra-tile xbar

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This commit is contained in:
Andrew Waterman 2017-09-19 17:49:27 -07:00
parent afad25fceb
commit aaad73f019
1 changed files with 16 additions and 13 deletions
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29
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -100,29 +100,32 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
val module: CanHaveScratchpadModule val module: CanHaveScratchpadModule
val cacheBlockBytes = p(CacheBlockBytes) val cacheBlockBytes = p(CacheBlockBytes)
val intOutputNode = tileParams.core.tileControlAddr.map(dummy => IntOutputNode())
val slaveNode = TLInputNode() // Up to three uses for this input node:
// 1) Frontend always exists, but may or may not have a scratchpad node
// 2) ScratchpadSlavePort always has a node, but only exists when the HellaCache has a scratchpad
// 3) BusErrorUnit sometimes has a node
val fg = LazyModule(new TLFragmenter(tileParams.core.fetchBytes, cacheBlockBytes, earlyAck=true))
val ww = LazyModule(new TLWidthWidget(xBytes))
val scratch = tileParams.dcache.flatMap { d => d.scratch.map(s => val scratch = tileParams.dcache.flatMap { d => d.scratch.map(s =>
LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics))) LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics)))
} }
val intOutputNode = tileParams.core.tileControlAddr.map(dummy => IntOutputNode())
val busErrorUnit = tileParams.core.tileControlAddr map { a => val busErrorUnit = tileParams.core.tileControlAddr map { a =>
val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a))) val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a)))
intOutputNode.get := beu.intNode intOutputNode.get := beu.intNode
beu beu
} }
// connect any combination of ITIM, DTIM, and BusErrorUnit
val slaveNode = TLInputNode()
DisableMonitors { implicit p => DisableMonitors { implicit p =>
frontend.slaveNode :*= fg.node val xbarPorts =
fg.node :*= ww.node scratch.map(lm => (lm.node, xBytes)) ++
ww.node :*= slaveNode busErrorUnit.map(lm => (lm.node, xBytes)) ++
scratch foreach { lm => lm.node := TLFragmenter(xBytes, cacheBlockBytes, earlyAck=true)(slaveNode) } tileParams.icache.flatMap(icache => icache.itimAddr.map(a => (frontend.slaveNode, tileParams.core.fetchBytes)))
busErrorUnit foreach { lm => lm.node := TLFragmenter(xBytes, cacheBlockBytes, earlyAck=true)(slaveNode) }
if (xbarPorts.nonEmpty) {
val xbar = LazyModule(new TLXbar)
xbar.node := TLFIFOFixer()(TLFragmenter(xBytes, cacheBlockBytes, earlyAck=true)(slaveNode))
xbarPorts.foreach { case (port, bytes) =>
port := (if (bytes == xBytes) xbar.node else TLFragmenter(bytes, xBytes, earlyAck=true)(TLWidthWidget(xBytes)(xbar.node)))
}
}
} }
def findScratchpadFromICache: Option[AddressSet] = scratch.map { s => def findScratchpadFromICache: Option[AddressSet] = scratch.map { s =>