Merge pull request #312 from ucb-bar/tl2-cheap-address-decode
Tl2 cheap address decode
This commit is contained in:
Wesley W. Terpstra
GitHub
commit
aa956c0108
@ -77,7 +77,7 @@ object GenerateGlobalAddrMap {
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(if (manager.executable) AddrMapProt.X else 0), cacheable)
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val multi = manager.address.size > 1
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manager.address.zipWithIndex.map { case (address, i) =>
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require (!address.strided) // TL1 can't do this
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require (address.contiguous) // TL1 needs this
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val name = manager.name + (if (multi) ".%d".format(i) else "")
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AddrMapEntry(name, MemRange(address.base, address.mask+1, attr))
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}
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@ -231,7 +231,7 @@ class TLEdgeOut(
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// Transfers
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def Acquire(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
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require (manager.anySupportAcquire)
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val legal = manager.supportsAcquire(toAddress, lgSize)
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val legal = manager.supportsAcquireFast(toAddress, lgSize)
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val a = Wire(new TLBundleA(bundle))
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a.opcode := TLMessages.Acquire
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a.param := growPermissions
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@ -245,7 +245,7 @@ class TLEdgeOut(
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def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt) = {
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require (manager.anySupportAcquire)
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val legal = manager.supportsAcquire(toAddress, lgSize)
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val legal = manager.supportsAcquireFast(toAddress, lgSize)
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val c = Wire(new TLBundleC(bundle))
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c.opcode := TLMessages.Release
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c.param := shrinkPermissions
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@ -260,7 +260,7 @@ class TLEdgeOut(
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def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt) = {
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require (manager.anySupportAcquire)
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val legal = manager.supportsAcquire(toAddress, lgSize)
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val legal = manager.supportsAcquireFast(toAddress, lgSize)
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val c = Wire(new TLBundleC(bundle))
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c.opcode := TLMessages.ReleaseData
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c.param := shrinkPermissions
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@ -308,7 +308,7 @@ class TLEdgeOut(
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// Accesses
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def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
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require (manager.anySupportGet)
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val legal = manager.supportsGet(toAddress, lgSize)
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val legal = manager.supportsGetFast(toAddress, lgSize)
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val a = Wire(new TLBundleA(bundle))
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a.opcode := TLMessages.Get
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a.param := UInt(0)
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@ -322,7 +322,7 @@ class TLEdgeOut(
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def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt) = {
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require (manager.anySupportPutFull)
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val legal = manager.supportsPutFull(toAddress, lgSize)
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val legal = manager.supportsPutFullFast(toAddress, lgSize)
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val a = Wire(new TLBundleA(bundle))
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a.opcode := TLMessages.PutFullData
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a.param := UInt(0)
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@ -336,7 +336,7 @@ class TLEdgeOut(
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def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask : UInt) = {
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require (manager.anySupportPutPartial)
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val legal = manager.supportsPutPartial(toAddress, lgSize)
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val legal = manager.supportsPutPartialFast(toAddress, lgSize)
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val a = Wire(new TLBundleA(bundle))
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a.opcode := TLMessages.PutPartialData
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a.param := UInt(0)
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@ -350,7 +350,7 @@ class TLEdgeOut(
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def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt) = {
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require (manager.anySupportArithmetic)
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val legal = manager.supportsArithmetic(toAddress, lgSize)
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val legal = manager.supportsArithmeticFast(toAddress, lgSize)
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val a = Wire(new TLBundleA(bundle))
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a.opcode := TLMessages.ArithmeticData
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a.param := atomic
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@ -364,7 +364,7 @@ class TLEdgeOut(
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def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt) = {
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require (manager.anySupportLogical)
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val legal = manager.supportsLogical(toAddress, lgSize)
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val legal = manager.supportsLogicalFast(toAddress, lgSize)
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val a = Wire(new TLBundleA(bundle))
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a.opcode := TLMessages.LogicalData
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a.param := atomic
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@ -378,7 +378,7 @@ class TLEdgeOut(
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def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
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require (manager.anySupportHint)
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val legal = manager.supportsHint(toAddress, lgSize)
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val legal = manager.supportsHintFast(toAddress, lgSize)
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val a = Wire(new TLBundleA(bundle))
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a.opcode := TLMessages.Hint
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a.param := param
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@ -445,7 +445,7 @@ class TLEdgeIn(
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// Transfers
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def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
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require (client.anySupportProbe)
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val legal = client.supportsProbe(fromAddress, lgSize)
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val legal = client.supportsProbe(toSource, lgSize)
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val b = Wire(new TLBundleB(bundle))
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b.opcode := TLMessages.Probe
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b.param := capPermissions
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@ -189,7 +189,7 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
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val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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// If this is infront of a single manager, these become constants
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val find = manager.find(edgeIn.address(in.a.bits))
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val find = manager.findFast(edgeIn.address(in.a.bits))
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val maxLgArithmetic = Mux1H(find, maxLgArithmetics)
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val maxLgLogical = Mux1H(find, maxLgLogicals)
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val maxLgGet = Mux1H(find, maxLgGets)
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@ -163,10 +163,12 @@ class TLFuzzer(
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edge.Hint(src, addr, size, UInt(0))
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} else { (glegal, gbits) }
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val legal_dest = edge.manager.containsSafe(addr)
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// Pick a specific message to try to send
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val a_type_sel = noiseMaker(3, inc)
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val legal = MuxLookup(a_type_sel, glegal, Seq(
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val legal = legal_dest && MuxLookup(a_type_sel, glegal, Seq(
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UInt("b000") -> glegal,
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UInt("b001") -> pflegal,
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UInt("b010") -> pplegal,
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@ -218,14 +220,18 @@ class ClockDivider extends BlackBox {
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class TLFuzzRAM extends LazyModule
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{
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val model = LazyModule(new TLRAMModel)
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val ram = LazyModule(new TLRAM(AddressSet(0, 0x3ff)))
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val ram = LazyModule(new TLRAM(AddressSet(0x800, 0x7ff)))
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val ram2 = LazyModule(new TLRAM(AddressSet(0, 0x3ff), beatBytes = 16))
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val gpio = LazyModule(new RRTest1(0x400))
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val xbar = LazyModule(new TLXbar)
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val xbar2= LazyModule(new TLXbar)
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val fuzz = LazyModule(new TLFuzzer(5000))
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val cross = LazyModule(new TLAsyncCrossing)
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model.node := fuzz.node
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xbar.node := TLWidthWidget(TLHintHandler(model.node), 16)
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xbar2.node := model.node
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ram2.node := TLFragmenter(xbar2.node, 16, 256)
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xbar.node := TLWidthWidget(TLHintHandler(xbar2.node), 16)
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cross.node := TLFragmenter(TLBuffer(xbar.node), 4, 256)
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ram.node := cross.node
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gpio.node := TLFragmenter(TLBuffer(xbar.node), 4, 32)
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@ -45,7 +45,7 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
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// Who wants what?
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val address = edgeIn.address(in.a.bits)
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val handleA = if (passthrough) !edgeOut.manager.supportsHint(address, edgeIn.size(in.a.bits)) else Bool(true)
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val handleA = if (passthrough) !edgeOut.manager.supportsHintFast(address, edgeIn.size(in.a.bits)) else Bool(true)
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val hintBitsAtA = handleA && in.a.bits.opcode === TLMessages.Hint
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val hintWantsD = in.a.valid && hintBitsAtA
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val outerWantsD = out.d.valid
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@ -57,7 +57,7 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
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assert (!hintHoldsD || hintWantsD)
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in.d.valid := Mux(hintWinsD, hintWantsD, outerWantsD)
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in.d.bits := Mux(hintWinsD, edgeIn.HintAck(in.a.bits, edgeOut.manager.findId(address)), out.d.bits)
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in.d.bits := Mux(hintWinsD, edgeIn.HintAck(in.a.bits, edgeOut.manager.findIdStartFast(address)), out.d.bits)
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out.d.ready := in.d.ready && !hintHoldsD
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in.a.ready := Mux(hintBitsAtA, hintWinsD && in.d.ready, out.a.ready)
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@ -21,9 +21,19 @@ object IntRange
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implicit def apply(end: Int): IntRange = apply(0, end)
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}
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case class IntSourceParameters(device: String, range: IntRange)
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case class IntSourceParameters(
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range: IntRange,
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nodePath: Seq[IntBaseNode] = Seq())
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{
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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}
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case class IntSinkParameters(
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nodePath: Seq[IntBaseNode] = Seq())
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{
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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}
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case class IntSinkPortParameters()
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case class IntSourcePortParameters(sources: Seq[IntSourceParameters])
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{
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val num = sources.map(_.range.size).sum
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@ -32,6 +42,9 @@ case class IntSourcePortParameters(sources: Seq[IntSourceParameters])
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// The interrupts must perfectly cover the range
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require (sources.map(_.range.end).max == num)
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}
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case class IntSinkPortParameters(sinks: Seq[IntSinkParameters])
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case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters)
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object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, IntEdge, IntEdge, Vec[Bool]]
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@ -52,16 +65,21 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In
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// Cannot use bulk connect, because the widths could differ
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(bo zip bi) foreach { case (o, i) => i := o }
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}
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override def mixO(po: IntSourcePortParameters, node: IntBaseNode): IntSourcePortParameters =
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po.copy(sources = po.sources.map { s => s.copy (nodePath = node +: s.nodePath) })
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override def mixI(pi: IntSinkPortParameters, node: IntBaseNode): IntSinkPortParameters =
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pi.copy(sinks = pi.sinks.map { s => s.copy (nodePath = node +: s.nodePath) })
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}
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case class IntIdentityNode() extends IdentityNode(IntImp)
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case class IntOutputNode() extends OutputNode(IntImp)
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case class IntInputNode() extends InputNode(IntImp)
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case class IntSourceNode(device: String, num: Int) extends SourceNode(IntImp)(
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IntSourcePortParameters(Seq(IntSourceParameters(device, num))),
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(if (num == 0) 0 else 1) to 1)
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case class IntSinkNode() extends SinkNode(IntImp)(IntSinkPortParameters())
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case class IntSourceNode(num: Int) extends SourceNode(IntImp)(
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IntSourcePortParameters(Seq(IntSourceParameters(num))), (if (num == 0) 0 else 1) to 1)
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case class IntSinkNode() extends SinkNode(IntImp)(
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IntSinkPortParameters(Seq(IntSinkParameters())))
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case class IntAdapterNode(
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sourceFn: Seq[IntSourcePortParameters] => IntSourcePortParameters,
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@ -75,7 +93,7 @@ class IntXbar extends LazyModule
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val intnode = IntAdapterNode(
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numSourcePorts = 1 to 1, // does it make sense to have more than one interrupt sink?
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numSinkPorts = 1 to 128,
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sinkFn = { _ => IntSinkPortParameters() },
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sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
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sourceFn = { seq =>
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IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map {
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case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
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@ -24,7 +24,7 @@ object TLMonitor
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val mask = edge.full_mask(bundle)
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when (bundle.opcode === TLMessages.Acquire) {
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assert (edge.manager.supportsAcquire(edge.address(bundle), bundle.size), "'A' channel carries Acquire type unsupported by manager" + extra)
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assert (edge.manager.supportsAcquireSafe(edge.address(bundle), bundle.size), "'A' channel carries Acquire type unsupported by manager" + extra)
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assert (source_ok, "'A' channel Acquire carries invalid source ID" + extra)
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assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), "'A' channel Acquire smaller than a beat" + extra)
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assert (is_aligned, "'A' channel Acquire address not aligned to size" + extra)
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@ -33,7 +33,7 @@ object TLMonitor
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}
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when (bundle.opcode === TLMessages.Get) {
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assert (edge.manager.supportsGet(edge.address(bundle), bundle.size), "'A' channel carries Get type unsupported by manager" + extra)
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assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), "'A' channel carries Get type unsupported by manager" + extra)
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assert (source_ok, "'A' channel Get carries invalid source ID" + extra)
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assert (is_aligned, "'A' channel Get address not aligned to size" + extra)
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assert (bundle.param === UInt(0), "'A' channel Get carries invalid param" + extra)
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@ -41,7 +41,7 @@ object TLMonitor
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}
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when (bundle.opcode === TLMessages.PutFullData) {
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assert (edge.manager.supportsPutFull(edge.address(bundle), bundle.size), "'A' channel carries PutFull type unsupported by manager" + extra)
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assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type unsupported by manager" + extra)
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assert (source_ok, "'A' channel PutFull carries invalid source ID" + extra)
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assert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
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assert (bundle.param === UInt(0), "'A' channel PutFull carries invalid param" + extra)
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@ -49,7 +49,7 @@ object TLMonitor
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}
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when (bundle.opcode === TLMessages.PutPartialData) {
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assert (edge.manager.supportsPutPartial(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type unsupported by manager" + extra)
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assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type unsupported by manager" + extra)
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assert (source_ok, "'A' channel PutPartial carries invalid source ID" + extra)
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assert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
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assert (bundle.param === UInt(0), "'A' channel PutPartial carries invalid param" + extra)
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@ -57,7 +57,7 @@ object TLMonitor
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}
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when (bundle.opcode === TLMessages.ArithmeticData) {
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assert (edge.manager.supportsArithmetic(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type unsupported by manager" + extra)
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assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type unsupported by manager" + extra)
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assert (source_ok, "'A' channel Arithmetic carries invalid source ID" + extra)
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assert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
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assert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
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@ -65,7 +65,7 @@ object TLMonitor
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}
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when (bundle.opcode === TLMessages.LogicalData) {
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assert (edge.manager.supportsLogical(edge.address(bundle), bundle.size), "'A' channel carries Logical type unsupported by manager" + extra)
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assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type unsupported by manager" + extra)
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assert (source_ok, "'A' channel Logical carries invalid source ID" + extra)
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assert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
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assert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
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@ -73,7 +73,7 @@ object TLMonitor
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}
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when (bundle.opcode === TLMessages.Hint) {
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assert (edge.manager.supportsHint(edge.address(bundle), bundle.size), "'A' channel carries Hint type unsupported by manager" + extra)
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assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type unsupported by manager" + extra)
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assert (source_ok, "'A' channel Hint carries invalid source ID" + extra)
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assert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
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assert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
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@ -84,7 +84,7 @@ object TLMonitor
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assert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
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// Reuse these subexpressions to save some firrtl lines
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val address_ok = edge.manager.contains(bundle.source)
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val address_ok = edge.manager.containsSafe(edge.address(bundle))
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val is_aligned = edge.isHiAligned(bundle.addr_hi, bundle.size)
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val mask = edge.full_mask(bundle)
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@ -150,7 +150,7 @@ object TLMonitor
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val source_ok = edge.client.contains(bundle.source)
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val is_aligned = edge.isHiAligned(bundle.addr_hi, bundle.size) && edge.isLoAligned(bundle.addr_lo, bundle.size)
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val address_ok = edge.manager.contains(bundle.source)
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val address_ok = edge.manager.containsSafe(edge.address(bundle))
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when (bundle.opcode === TLMessages.ProbeAck) {
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assert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
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@ -171,7 +171,7 @@ object TLMonitor
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}
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when (bundle.opcode === TLMessages.Release) {
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assert (edge.manager.supportsAcquire(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
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assert (edge.manager.supportsAcquireSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
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assert (source_ok, "'C' channel Release carries invalid source ID" + extra)
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assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), "'C' channel Release smaller than a beat" + extra)
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assert (is_aligned, "'C' channel Release address not aligned to size" + extra)
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@ -180,7 +180,7 @@ object TLMonitor
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}
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when (bundle.opcode === TLMessages.ReleaseData) {
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assert (edge.manager.supportsAcquire(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
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assert (edge.manager.supportsAcquireSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
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assert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
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assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), "'C' channel ReleaseData smaller than a beat" + extra)
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assert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
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@ -82,26 +82,29 @@ case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
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{
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// Forbid misaligned base address (and empty sets)
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require ((base & mask) == 0)
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require (base >= 0) // TL2 address widths are not fixed => negative is ambiguous
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// We do allow negative mask (=> ignore all high bits)
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def contains(x: BigInt) = ~(~(x ^ base) | mask) == 0
|
||||
def contains(x: UInt) = ~(~(x ^ UInt(base)) | UInt(mask)) === UInt(0)
|
||||
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
|
||||
def contains(x: UInt) = ((x ^ UInt(base)).zext() & SInt(~mask)) === SInt(0)
|
||||
|
||||
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
|
||||
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
|
||||
|
||||
// contains iff bitwise: x.mask => mask && contains(x.base)
|
||||
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
|
||||
// 1 less than the number of bytes to which the manager should be aligned
|
||||
def alignment1 = ((mask + 1) & ~mask) - 1
|
||||
def max = base | mask
|
||||
|
||||
// A strided slave serves discontiguous ranges
|
||||
def strided = alignment1 != mask
|
||||
// The number of bytes to which the manager must be aligned
|
||||
def alignment = ((mask + 1) & ~mask)
|
||||
// Is this a contiguous memory range
|
||||
def contiguous = alignment == mask+1
|
||||
|
||||
def finite = mask >= 0
|
||||
def max = { require (finite); base | mask }
|
||||
|
||||
// Widen the match function to ignore all bits in imask
|
||||
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
|
||||
|
||||
// AddressSets have one natural Ordering (the containment order)
|
||||
// AddressSets have one natural Ordering (the containment order, if contiguous)
|
||||
def compare(x: AddressSet) = {
|
||||
val primary = (this.base - x.base).signum // smallest address first
|
||||
val secondary = (x.mask - this.mask).signum // largest mask first
|
||||
@ -109,7 +112,13 @@ case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
|
||||
}
|
||||
|
||||
// We always want to see things in hex
|
||||
override def toString() = "AddressSet(0x%x, 0x%x)".format(base, mask)
|
||||
override def toString() = {
|
||||
if (mask >= 0) {
|
||||
"AddressSet(0x%x, 0x%x)".format(base, mask)
|
||||
} else {
|
||||
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
case class TLManagerParameters(
|
||||
@ -130,6 +139,7 @@ case class TLManagerParameters(
|
||||
fifoId: Option[Int] = None,
|
||||
customDTS: Option[String]= None)
|
||||
{
|
||||
address.foreach { a => require (a.finite) }
|
||||
address.combinations(2).foreach({ case Seq(x,y) =>
|
||||
require (!x.overlaps(y))
|
||||
})
|
||||
@ -144,12 +154,13 @@ case class TLManagerParameters(
|
||||
supportsPutFull.max,
|
||||
supportsPutPartial.max).max
|
||||
|
||||
val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
|
||||
|
||||
// Generate the config string (in future device tree)
|
||||
lazy val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
|
||||
lazy val dts = customDTS.getOrElse {
|
||||
val header = s"${name} {\n"
|
||||
val middle = address.map { a =>
|
||||
require (!a.strided) // Config String does not support this
|
||||
require (a.contiguous) // Config String is not so flexible
|
||||
" addr 0x%x;\n size 0x%x;\n".format(a.base, a.mask+1)
|
||||
}
|
||||
val footer = "}\n"
|
||||
@ -158,7 +169,7 @@ case class TLManagerParameters(
|
||||
|
||||
// The device had better not support a transfer larger than it's alignment
|
||||
address.foreach({ case a =>
|
||||
require (a.alignment1 >= maxTransfer-1)
|
||||
require (a.alignment >= maxTransfer)
|
||||
})
|
||||
}
|
||||
|
||||
@ -198,41 +209,59 @@ case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes
|
||||
val anySupportPutPartial = managers.map(!_.supportsPutPartial.none).reduce(_ || _)
|
||||
val anySupportHint = managers.map(!_.supportsHint.none) .reduce(_ || _)
|
||||
|
||||
// Which bits suffice to distinguish between all managers
|
||||
lazy val routingMask = AddressDecoder(managers.map(_.address))
|
||||
|
||||
// These return Option[TLManagerParameters] for your convenience
|
||||
def find(address: BigInt) = managers.find(_.address.exists(_.contains(address)))
|
||||
def findById(id: Int) = managers.find(_.sinkId.contains(id))
|
||||
|
||||
// Synthesizable lookup methods
|
||||
def find(address: UInt) = Vec(managers.map(_.address.map(_.contains(address)).reduce(_ || _)))
|
||||
def findById(id: UInt) = Vec(managers.map(_.sinkId.contains(id)))
|
||||
def findId(address: UInt) = Mux1H(find(address), managers.map(m => UInt(m.sinkId.start)))
|
||||
def findIdStartSafe(address: UInt) = Mux1H(findSafe(address), managers.map(m => UInt(m.sinkId.start)))
|
||||
def findIdStartFast(address: UInt) = Mux1H(findFast(address), managers.map(m => UInt(m.sinkId.start)))
|
||||
def findIdEndSafe(address: UInt) = Mux1H(findSafe(address), managers.map(m => UInt(m.sinkId.end)))
|
||||
def findIdEndFast(address: UInt) = Mux1H(findFast(address), managers.map(m => UInt(m.sinkId.end)))
|
||||
|
||||
// The safe version will check the entire address
|
||||
def findSafe(address: UInt) = Vec(managers.map(_.address.map(_.contains(address)).reduce(_ || _)))
|
||||
// The fast version assumes the address is valid
|
||||
def findFast(address: UInt) = Vec(managers.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
|
||||
|
||||
// Note: returns the actual fifoId + 1 or 0 if None
|
||||
def findFifoId(address: UInt) = Mux1H(find(address), managers.map(m => UInt(m.fifoId.map(_+1).getOrElse(0))))
|
||||
def hasFifoId(address: UInt) = Mux1H(find(address), managers.map(m => Bool(m.fifoId.isDefined)))
|
||||
|
||||
lazy val addressMask = AddressDecoder(managers.map(_.address))
|
||||
// !!! need a cheaper version of find, where we assume a valid address match exists
|
||||
def findFifoIdSafe(address: UInt) = Mux1H(findSafe(address), managers.map(m => UInt(m.fifoId.map(_+1).getOrElse(0))))
|
||||
def findFifoIdFast(address: UInt) = Mux1H(findFast(address), managers.map(m => UInt(m.fifoId.map(_+1).getOrElse(0))))
|
||||
def hasFifoIdSafe(address: UInt) = Mux1H(findSafe(address), managers.map(m => Bool(m.fifoId.isDefined)))
|
||||
def hasFifoIdFast(address: UInt) = Mux1H(findFast(address), managers.map(m => Bool(m.fifoId.isDefined)))
|
||||
|
||||
// Does this Port manage this ID/address?
|
||||
def contains(address: UInt) = find(address).reduce(_ || _)
|
||||
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
|
||||
// containsFast would be useless; it could always be true
|
||||
def containsById(id: UInt) = findById(id).reduce(_ || _)
|
||||
|
||||
private def safety_helper(member: TLManagerParameters => TransferSizes)(address: UInt, lgSize: UInt) = {
|
||||
private def safety_helper(member: TLManagerParameters => TransferSizes, select: UInt => Vec[Bool])(address: UInt, lgSize: UInt) = {
|
||||
val allSame = managers.map(member(_) == member(managers(0))).reduce(_ && _)
|
||||
if (allSame) member(managers(0)).containsLg(lgSize) else {
|
||||
Mux1H(find(address), managers.map(member(_).containsLg(lgSize)))
|
||||
Mux1H(select(address), managers.map(member(_).containsLg(lgSize)))
|
||||
}
|
||||
}
|
||||
|
||||
// Check for support of a given operation at a specific address
|
||||
val supportsAcquire = safety_helper(_.supportsAcquire) _
|
||||
val supportsArithmetic = safety_helper(_.supportsArithmetic) _
|
||||
val supportsLogical = safety_helper(_.supportsLogical) _
|
||||
val supportsGet = safety_helper(_.supportsGet) _
|
||||
val supportsPutFull = safety_helper(_.supportsPutFull) _
|
||||
val supportsPutPartial = safety_helper(_.supportsPutPartial) _
|
||||
val supportsHint = safety_helper(_.supportsHint) _
|
||||
val supportsAcquireSafe = safety_helper(_.supportsAcquire, findSafe) _
|
||||
val supportsArithmeticSafe = safety_helper(_.supportsArithmetic, findSafe) _
|
||||
val supportsLogicalSafe = safety_helper(_.supportsLogical, findSafe) _
|
||||
val supportsGetSafe = safety_helper(_.supportsGet, findSafe) _
|
||||
val supportsPutFullSafe = safety_helper(_.supportsPutFull, findSafe) _
|
||||
val supportsPutPartialSafe = safety_helper(_.supportsPutPartial, findSafe) _
|
||||
val supportsHintSafe = safety_helper(_.supportsHint, findSafe) _
|
||||
|
||||
val supportsAcquireFast = safety_helper(_.supportsAcquire, findFast) _
|
||||
val supportsArithmeticFast = safety_helper(_.supportsArithmetic, findFast) _
|
||||
val supportsLogicalFast = safety_helper(_.supportsLogical, findFast) _
|
||||
val supportsGetFast = safety_helper(_.supportsGet, findFast) _
|
||||
val supportsPutFullFast = safety_helper(_.supportsPutFull, findFast) _
|
||||
val supportsPutPartialFast = safety_helper(_.supportsPutPartial, findFast) _
|
||||
val supportsHintFast = safety_helper(_.supportsHint, findFast) _
|
||||
}
|
||||
|
||||
case class TLClientParameters(
|
||||
@ -256,6 +285,8 @@ case class TLClientParameters(
|
||||
supportsGet.max,
|
||||
supportsPutFull.max,
|
||||
supportsPutPartial.max).max
|
||||
|
||||
val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
|
||||
}
|
||||
|
||||
case class TLClientPortParameters(clients: Seq[TLClientParameters]) {
|
||||
|
||||
@ -119,7 +119,7 @@ class TLRAMModel extends LazyModule
|
||||
val a_addr_hi = a.addr_hi | (a_beats1 & ~a_counter1)
|
||||
val a_base = edge.address(a)
|
||||
val a_mask = edge.mask(a_base, a_size)
|
||||
val a_fifo = edge.manager.hasFifoId(a_base)
|
||||
val a_fifo = edge.manager.hasFifoIdFast(a_base)
|
||||
|
||||
// Grab the concurrency state we need
|
||||
val a_inc_bytes = inc_bytes.map(_.read(a_addr_hi))
|
||||
@ -203,7 +203,7 @@ class TLRAMModel extends LazyModule
|
||||
val d_base = d_flight.base
|
||||
val d_addr_hi = d_base >> shift | (d_beats1 & ~d_counter1)
|
||||
val d_mask = edge.mask(d_base, d_size)
|
||||
val d_fifo = edge.manager.hasFifoId(d_flight.base)
|
||||
val d_fifo = edge.manager.hasFifoIdFast(d_flight.base)
|
||||
|
||||
// Grab the concurrency state we need
|
||||
val d_inc_bytes = inc_bytes.map(_.read(d_addr_hi))
|
||||
@ -222,7 +222,8 @@ class TLRAMModel extends LazyModule
|
||||
|
||||
// Check the response is correct
|
||||
assert (d_size === d_flight.size)
|
||||
assert (edge.manager.findId(d_flight.base) === d.sink)
|
||||
assert (edge.manager.findIdStartFast(d_flight.base) <= d.sink)
|
||||
assert (edge.manager.findIdEndFast (d_flight.base) > d.sink)
|
||||
// addr_lo is allowed to differ
|
||||
|
||||
when (d_flight.opcode === TLMessages.Hint) {
|
||||
|
||||
@ -12,7 +12,7 @@ class TLRegisterNode(address: AddressSet, concurrency: Option[Int] = None, beatB
|
||||
supportsPutFull = TransferSizes(1, beatBytes),
|
||||
fifoId = Some(0))) // requests are handled in order
|
||||
{
|
||||
require (!address.strided)
|
||||
require (address.contiguous)
|
||||
|
||||
// Calling this method causes the matching TL2 bundle to be
|
||||
// configured to route all requests to the listed RegFields.
|
||||
@ -75,7 +75,7 @@ object TLRegisterNode
|
||||
abstract class TLRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Option[Int], beatBytes: Int, undefZero: Boolean) extends LazyModule
|
||||
{
|
||||
val node = TLRegisterNode(address, concurrency, beatBytes, undefZero)
|
||||
val intnode = IntSourceNode(name + s" @ ${address.base}", interrupts)
|
||||
val intnode = IntSourceNode(interrupts)
|
||||
}
|
||||
|
||||
case class TLRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[TLBundle])
|
||||
|
||||
@ -75,6 +75,23 @@ class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extend
|
||||
val inputIdRanges = mapInputIds(node.edgesIn.map(_.client))
|
||||
val outputIdRanges = mapOutputIds(node.edgesOut.map(_.manager))
|
||||
|
||||
// Find a good mask for address decoding
|
||||
val port_addrs = node.edgesOut.map(_.manager.managers.map(_.address).flatten)
|
||||
val routingMask = AddressDecoder(port_addrs)
|
||||
val route_addrs = port_addrs.map(_.map(_.widen(~routingMask)).distinct)
|
||||
val outputPorts = route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))
|
||||
|
||||
// Print the mapping
|
||||
if (false) {
|
||||
println("Xbar mapping:")
|
||||
route_addrs.foreach { p =>
|
||||
print(" ")
|
||||
p.foreach { a => print(s" ${a}") }
|
||||
println("")
|
||||
}
|
||||
println("--")
|
||||
}
|
||||
|
||||
// We need an intermediate size of bundle with the widest possible identifiers
|
||||
val wide_bundle = io.in(0).params.union(io.out(0).params)
|
||||
|
||||
@ -145,9 +162,13 @@ class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extend
|
||||
in(i).e.ready := Mux1C(grantedEIO(i), out.map(_.e.ready))
|
||||
}
|
||||
|
||||
val requestAIO = Vec(in.map { i => Vec(node.edgesOut.map { o => i.a.valid && o.manager.contains(o.address(i.a.bits)) }) })
|
||||
val addressA = (in zip node.edgesIn) map { case (i, e) => (i.a.valid, e.address(i.a.bits)) }
|
||||
val addressC = (in zip node.edgesIn) map { case (i, e) => (i.c.valid, e.address(i.c.bits)) }
|
||||
|
||||
val requestAIO = Vec(addressA.map { i => Vec(outputPorts.map { o => i._1 && o(i._2) }) })
|
||||
val requestCIO = Vec(addressC.map { i => Vec(outputPorts.map { o => i._1 && o(i._2) }) })
|
||||
|
||||
val requestBOI = Vec(out.map { o => Vec(inputIdRanges.map { i => o.b.valid && i.contains(o.b.bits.source) }) })
|
||||
val requestCIO = Vec(in.map { i => Vec(node.edgesOut.map { o => i.c.valid && o.manager.contains(o.address(i.c.bits)) }) })
|
||||
val requestDOI = Vec(out.map { o => Vec(inputIdRanges.map { i => o.d.valid && i.contains(o.d.bits.source) }) })
|
||||
val requestEIO = Vec(in.map { i => Vec(outputIdRanges.map { o => i.e.valid && o.contains(i.e.bits.sink) }) })
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user