riscv/rocket-chip
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rename queue to Queue

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fixes build with case-insensitive file system
This commit is contained in:
Andrew Waterman
2012-08-08 22:11:32 -07:00
parent 115c25c34b
commit aa7fd1f40b
2 changed files with 3 additions and 3 deletions
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2
uncore/llc.scala
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@@ -245,7 +245,7 @@ class LLCData(latency: Int, sets: Int, ways: Int, leaf: Mem[Bits]) extends Compo
val isWriteback = Bool()
override def clone = new QEntry().asInstanceOf[this.type]
}
val q = (new queue(latency+2)) { new QEntry }
val q = (new Queue(latency+2)) { new QEntry }
val qReady = q.io.count <= UFix(q.entries-latency-1)
val valid = Reg(resetVal = Bool(false))
val req = Reg() { io.req.bits.clone }

4
uncore/uncore.scala
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@@ -336,8 +336,8 @@ class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceH
}
}
val p_rep_data_dep_list = List.fill(ntiles)((new queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY
val x_init_data_dep_list = List.fill(ntiles)((new queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY
val p_rep_data_dep_list = List.fill(ntiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY
val x_init_data_dep_list = List.fill(ntiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY
// Free finished transactions
for( j <- 0 until ntiles ) {