riscv/rocket-chip
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HellaCache: users like to peep resp.data and resp.addr

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This commit is contained in:
Henry Cook 2017-10-02 19:01:05 -07:00
parent cedfb0e784
commit aa3a18222c
1 changed files with 2 additions and 0 deletions
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src/main/scala/rocket/HellaCache.scala
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@ -4,6 +4,7 @@
package freechips.rocketchip.rocket package freechips.rocketchip.rocket
import Chisel._ import Chisel._
import chisel3.experimental.dontTouch
import freechips.rocketchip.config.{Parameters, Field} import freechips.rocketchip.config.{Parameters, Field}
import freechips.rocketchip.coreplex._ import freechips.rocketchip.coreplex._
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
@ -184,6 +185,7 @@ class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
implicit val edge = outer.node.edges.out(0) implicit val edge = outer.node.edges.out(0)
val (tl_out, _) = outer.node.out(0) val (tl_out, _) = outer.node.out(0)
val io = IO(new HellaCacheBundle(outer)) val io = IO(new HellaCacheBundle(outer))
dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some
private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allUncacheable) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allUncacheable)
fifoManagers.foreach { m => fifoManagers.foreach { m =>