riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2 RAMModel: include name of test in output

Browse Source
This commit is contained in:
Wesley W. Terpstra 2016-10-11 22:32:06 -07:00
parent 345eefd81b
commit a9a3f7dd4e
3 changed files with 8 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/uncore/axi4/Test.scala
View File

@ -17,7 +17,7 @@ class RRTest1(address: BigInt) extends AXI4RegisterRouter(address, 0, 32, 6, 4,
class AXI4LiteFuzzRAM extends LazyModule class AXI4LiteFuzzRAM extends LazyModule
{ {
val fuzz = LazyModule(new TLFuzzer(5000)) val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel) val model = LazyModule(new TLRAMModel("AXI4LiteFuzzRAM"))
val xbar = LazyModule(new TLXbar) val xbar = LazyModule(new TLXbar)
val gpio = LazyModule(new RRTest1(0x400)) val gpio = LazyModule(new RRTest1(0x400))
val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff))) val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
@ -40,7 +40,7 @@ class AXI4LiteFuzzRAMTest extends UnitTest(500000) {
class AXI4FullFuzzRAM extends LazyModule class AXI4FullFuzzRAM extends LazyModule
{ {
val fuzz = LazyModule(new TLFuzzer(5000)) val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel) val model = LazyModule(new TLRAMModel("AXI4FullFuzzRAM"))
val xbar = LazyModule(new TLXbar) val xbar = LazyModule(new TLXbar)
val gpio = LazyModule(new RRTest0(0x400)) val gpio = LazyModule(new RRTest0(0x400))
val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff))) val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))

2
src/main/scala/uncore/tilelink2/Fuzzer.scala
View File

@ -206,7 +206,7 @@ import unittest._
class TLFuzzRAM extends LazyModule class TLFuzzRAM extends LazyModule
{ {
val model = LazyModule(new TLRAMModel) val model = LazyModule(new TLRAMModel("TLFuzzRAM"))
val ram = LazyModule(new TLRAM(AddressSet(0x800, 0x7ff))) val ram = LazyModule(new TLRAM(AddressSet(0x800, 0x7ff)))
val ram2 = LazyModule(new TLRAM(AddressSet(0, 0x3ff), beatBytes = 16)) val ram2 = LazyModule(new TLRAM(AddressSet(0, 0x3ff), beatBytes = 16))
val gpio = LazyModule(new RRTest1(0x400)) val gpio = LazyModule(new RRTest1(0x400))

7
src/main/scala/uncore/tilelink2/RAMModel.scala
View File

@ -20,7 +20,7 @@ import diplomacy._
// put, get, getAck, putAck => ok: detected by getAck (it sees busy>0) impossible for FIFO // put, get, getAck, putAck => ok: detected by getAck (it sees busy>0) impossible for FIFO
// If FIFO, the getAck should check data even if its validity was wiped // If FIFO, the getAck should check data even if its validity was wiped
class TLRAMModel extends LazyModule class TLRAMModel(log: String = "") extends LazyModule
{ {
val node = TLIdentityNode() val node = TLIdentityNode()
@ -150,6 +150,7 @@ class TLRAMModel extends LazyModule
val busy = a_inc(i) - a_dec(i) - (!a_first).asUInt val busy = a_inc(i) - a_dec(i) - (!a_first).asUInt
val byte = a.data(8*(i+1)-1, 8*i) val byte = a.data(8*(i+1)-1, 8*i)
when (a.mask(i)) { when (a.mask(i)) {
printf(log + " ")
when (a.opcode === TLMessages.PutFullData) { printf("PF") } when (a.opcode === TLMessages.PutFullData) { printf("PF") }
when (a.opcode === TLMessages.PutPartialData) { printf("PP") } when (a.opcode === TLMessages.PutPartialData) { printf("PP") }
when (a.opcode === TLMessages.ArithmeticData) { printf("A ") } when (a.opcode === TLMessages.ArithmeticData) { printf("A ") }
@ -160,7 +161,7 @@ class TLRAMModel extends LazyModule
} }
when (a.opcode === TLMessages.Get) { when (a.opcode === TLMessages.Get) {
printf("G 0x%x - 0%x\n", a_base, a_base | UIntToOH1(a_size, addressBits)) printf(log + " G 0x%x - 0%x\n", a_base, a_base | UIntToOH1(a_size, addressBits))
} }
} }
@ -245,6 +246,7 @@ class TLRAMModel extends LazyModule
when (d_flight.opcode === TLMessages.PutFullData || d_flight.opcode === TLMessages.PutPartialData) { when (d_flight.opcode === TLMessages.PutFullData || d_flight.opcode === TLMessages.PutPartialData) {
assert (d.opcode === TLMessages.AccessAck) assert (d.opcode === TLMessages.AccessAck)
printf(log + " ")
when (d_flight.opcode === TLMessages.PutFullData) { printf("pf") } when (d_flight.opcode === TLMessages.PutFullData) { printf("pf") }
when (d_flight.opcode === TLMessages.PutPartialData) { printf("pp") } when (d_flight.opcode === TLMessages.PutPartialData) { printf("pp") }
printf(" 0x%x - 0x%x\n", d_base, d_base | UIntToOH1(d_size, addressBits)) printf(" 0x%x - 0x%x\n", d_base, d_base | UIntToOH1(d_size, addressBits))
@ -257,6 +259,7 @@ class TLRAMModel extends LazyModule
val shadow = Wire(init = d_shadow(i)) val shadow = Wire(init = d_shadow(i))
when (d_mask(i)) { when (d_mask(i)) {
val d_addr = d_addr_hi << shift | UInt(i) val d_addr = d_addr_hi << shift | UInt(i)
printf(log + " ")
when (d_flight.opcode === TLMessages.Get) { printf("g ") } when (d_flight.opcode === TLMessages.Get) { printf("g ") }
when (d_flight.opcode === TLMessages.ArithmeticData) { printf("a ") } when (d_flight.opcode === TLMessages.ArithmeticData) { printf("a ") }
when (d_flight.opcode === TLMessages.LogicalData) { printf("l ") } when (d_flight.opcode === TLMessages.LogicalData) { printf("l ") }