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tilelink2 RAMModel: include name of test in output

This commit is contained in:
Wesley W. Terpstra
2016-10-11 22:32:06 -07:00
parent 345eefd81b
commit a9a3f7dd4e
3 changed files with 8 additions and 5 deletions

View File

@ -206,7 +206,7 @@ import unittest._
class TLFuzzRAM extends LazyModule
{
val model = LazyModule(new TLRAMModel)
val model = LazyModule(new TLRAMModel("TLFuzzRAM"))
val ram = LazyModule(new TLRAM(AddressSet(0x800, 0x7ff)))
val ram2 = LazyModule(new TLRAM(AddressSet(0, 0x3ff), beatBytes = 16))
val gpio = LazyModule(new RRTest1(0x400))