tilelink2 RAMModel: include name of test in output
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@ -206,7 +206,7 @@ import unittest._
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class TLFuzzRAM extends LazyModule
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{
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val model = LazyModule(new TLRAMModel)
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val model = LazyModule(new TLRAMModel("TLFuzzRAM"))
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val ram = LazyModule(new TLRAM(AddressSet(0x800, 0x7ff)))
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val ram2 = LazyModule(new TLRAM(AddressSet(0, 0x3ff), beatBytes = 16))
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val gpio = LazyModule(new RRTest1(0x400))
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