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tilelink2 RAMModel: include name of test in output

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This commit is contained in:
Wesley W. Terpstra
2016-10-11 22:32:06 -07:00
parent 345eefd81b
commit a9a3f7dd4e
3 changed files with 8 additions and 5 deletions
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4
src/main/scala/uncore/axi4/Test.scala
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@ -17,7 +17,7 @@ class RRTest1(address: BigInt) extends AXI4RegisterRouter(address, 0, 32, 6, 4,
class AXI4LiteFuzzRAM extends LazyModule
{
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel)
val model = LazyModule(new TLRAMModel("AXI4LiteFuzzRAM"))
val xbar = LazyModule(new TLXbar)
val gpio = LazyModule(new RRTest1(0x400))
val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
@ -40,7 +40,7 @@ class AXI4LiteFuzzRAMTest extends UnitTest(500000) {
class AXI4FullFuzzRAM extends LazyModule
{
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel)
val model = LazyModule(new TLRAMModel("AXI4FullFuzzRAM"))
val xbar = LazyModule(new TLXbar)
val gpio = LazyModule(new RRTest0(0x400))
val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))