riscv/rocket-chip
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append config name to generated Makefrag filename

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This commit is contained in:
Yunsup Lee 2015-07-17 12:34:49 -07:00
parent 777facf91e
commit a99b1e3a01
4 changed files with 4 additions and 4 deletions
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2
emulator/Makefile
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@ -10,7 +10,7 @@ all: emulator-$(CONFIG)
debug: emulator-$(CONFIG)-debug debug: emulator-$(CONFIG)-debug
include $(base_dir)/Makefrag include $(base_dir)/Makefrag
-include generated-src/Makefrag -include generated-src/Makefrag-tests.$(CONFIG)
CXXFLAGS := $(CXXFLAGS) -std=c++11 -I$(RISCV)/include CXXFLAGS := $(CXXFLAGS) -std=c++11 -I$(RISCV)/include

2
fsim/Makefile
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@ -21,7 +21,7 @@ TB ?= rocketTestHarness
include $(base_dir)/Makefrag include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag include $(sim_dir)/Makefrag
-include $(generated_dir)/Makefrag -include $(generated_dir)/Makefrag-tests.$(CONFIG)
include $(base_dir)/vsim/Makefrag-sim include $(base_dir)/vsim/Makefrag-sim
all: $(simv) all: $(simv)

2
src/main/scala/Testing.scala
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@ -66,7 +66,7 @@ run-$kind-fast: $$(addprefix $$(output_dir)/, $$(addsuffix .run, $targets))
} else { "\n" } } else { "\n" }
} }
val f = createOutputFile("Makefrag") val f = createOutputFile("Makefrag-tests." + Driver.chiselConfigClassName.get)
f.write(List(gen("asm", asmSuites.values.toSeq), gen("bmark", bmarkSuites.values.toSeq)).mkString("\n")) f.write(List(gen("asm", asmSuites.values.toSeq), gen("bmark", bmarkSuites.values.toSeq)).mkString("\n"))
f.close f.close
} }

2
vsim/Makefile
View File

@ -21,7 +21,7 @@ TB ?= rocketTestHarness
include $(base_dir)/Makefrag include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag include $(sim_dir)/Makefrag
-include $(generated_dir)/Makefrag -include $(generated_dir)/Makefrag-tests.$(CONFIG)
include $(base_dir)/vsim/Makefrag-sim include $(base_dir)/vsim/Makefrag-sim
all: $(simv) all: $(simv)