riscv/rocket-chip
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Merge pull request #1035 from freechipsproject/big-paddr

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Fix paddrBits < xLen && paddrBits == vaddrBits case
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Andrew Waterman 2017-10-09 20:59:21 -07:00 committed by GitHub
commit a9686ab883
1 changed files with 3 additions and 1 deletions
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4
src/main/scala/tile/BaseTile.scala
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@ -48,7 +48,9 @@ trait HasTileParameters {
require(v == xLen || xLen > v && v > paddrBits)
v
} else {
paddrBits min xLen
// since virtual addresses sign-extend but physical addresses
// zero-extend, make room for a zero sign bit for physical addresses
(paddrBits + 1) min xLen
}
def paddrBits: Int = p(SharedMemoryTLEdge).bundle.addressBits
def vpnBits: Int = vaddrBits - pgIdxBits