riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

In TLBPermissions, merge across some region types

Browse Source 
We only care whether they have side effects or not.
This commit is contained in:
Andrew Waterman 2017-04-17 20:44:29 -07:00 committed by Andrew Waterman
parent 6de6f38894
commit a956b78dd2
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/rocket/TLBPermissions.scala
View File

@ -18,7 +18,7 @@ case class TLBPermissions(
object TLBPageLookup
{
private case class TLBFixedPermissions(
t: RegionType.T,
e: Boolean, // get-/put-effects
r: Boolean, // readable
w: Boolean, // writeable
x: Boolean, // executable
@ -48,7 +48,7 @@ object TLBPageLookup
require (m.supportsAcquireT || !m.supportsAcquireB, s"MemoryMap region ${m.name} supports AcquireB (cached read) but not AcquireT (cached write)... and rocket assumes this")
(m.address, TLBFixedPermissions(
t = m.regionType,
e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType,
r = m.supportsGet || m.supportsAcquireB, // if cached, never uses Get
w = m.supportsPutFull || m.supportsAcquireT, // if cached, never uses Put
x = m.executable,