Simplify AsyncResetRegVec and make AsyncResetReg companion object
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198a2d7022
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@ -45,7 +45,6 @@ class AsyncResetReg extends BlackBox {
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}
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}
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class SimpleRegIO(val w: Int) extends Bundle{
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class SimpleRegIO(val w: Int) extends Bundle{
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val d = UInt(INPUT, width = w)
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val d = UInt(INPUT, width = w)
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@ -55,29 +54,48 @@ class SimpleRegIO(val w: Int) extends Bundle{
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}
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}
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class AsyncResetRegVec(val w: Int, val init: Int) extends Module {
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class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
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val io = new SimpleRegIO(w)
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val io = new SimpleRegIO(w)
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val bb_q = Wire(UInt(width = w))
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val bb_d = Mux(io.en, io.d, io.q)
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val bb_d = Wire(UInt(width = w))
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val init_val = Wire(UInt(width = w))
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init_val := UInt(init, width = w)
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val async_regs = List.fill(w)(Module (new AsyncResetReg))
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val async_regs = List.fill(w)(Module (new AsyncResetReg))
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bb_q := (async_regs.map(_.io.q)).asUInt()
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io.q := async_regs.map(_.io.q).asUInt
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bb_d := Mux(io.en , io.d , bb_q)
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io.q := bb_q
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for ((reg, idx) <- async_regs.zipWithIndex) {
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for ((reg, idx) <- async_regs.zipWithIndex) {
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reg.io.clk := clock
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reg.io.clk := clock
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reg.io.rst := reset
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reg.io.rst := reset
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reg.io.init := init_val(idx)
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reg.io.init := Bool(((init >> idx) & 1) == 1)
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reg.io.d := bb_d(idx)
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reg.io.d := bb_d(idx)
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}
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}
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}
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}
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object AsyncResetReg {
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def apply(d: Bool, clk: Clock, rst: Bool, init: Bool): Bool = {
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val reg = Module(new AsyncResetReg)
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reg.io.d := d
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reg.io.clk := clk
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reg.io.rst := rst
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reg.io.init := init
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reg.io.q
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}
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def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, Bool(false))
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def apply(updateData: UInt, resetData: BigInt, enable: Bool): UInt = {
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val w = updateData.getWidth max resetData.bitLength
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val reg = Module(new AsyncResetRegVec(w, resetData))
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reg.io.d := updateData
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reg.io.en := enable
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reg.io.q
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}
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def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, Bool(true))
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def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, BigInt(0), enable)
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def apply(updateData: UInt): UInt = apply(updateData, BigInt(0), Bool(true))
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}
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