riscv/rocket-chip
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make sure merged voluntary releases are handled properly

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This commit is contained in:
Howard Mao 2016-06-27 11:40:32 -07:00
parent 354b81c8fe
commit a93a70c8ec
1 changed files with 4 additions and 4 deletions
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8
uncore/src/main/scala/trackers.scala
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@ -247,16 +247,16 @@ trait AcceptsVoluntaryReleases extends HasVoluntaryReleaseMetadataBuffer {
xact_vol_ir_r_type := io.irel().r_type xact_vol_ir_r_type := io.irel().r_type
xact_vol_ir_src := io.irel().client_id xact_vol_ir_src := io.irel().client_id
xact_vol_ir_client_xact_id := io.irel().client_xact_id xact_vol_ir_client_xact_id := io.irel().client_xact_id
// If this release has data, set all the pending bits except the first.
// Otherwise, clear all the pending bits
pending_irel_data := Mux(io.irel().hasMultibeatData(), pending_irel_data := Mux(io.irel().hasMultibeatData(),
dropPendingBitWhenBeatHasData(io.inner.release), dropPendingBitWhenBeatHasData(io.inner.release),
UInt(0)) UInt(0))
} .elsewhen (irel_same_xact) {
pending_irel_data := (pending_irel_data & dropPendingBitWhenBeatHasData(io.inner.release))
} }
} }
when (irel_is_merging) {
pending_irel_data := (pending_irel_data & dropPendingBitWhenBeatHasData(io.inner.release))
}
io.inner.grant.valid := Vec(s_wb_req, s_wb_resp, s_inner_probe, s_busy).contains(state) && io.inner.grant.valid := Vec(s_wb_req, s_wb_resp, s_inner_probe, s_busy).contains(state) &&
vol_ignt_counter.pending && vol_ignt_counter.pending &&
!(pending_irel_data.orR || block_vol_ignt) !(pending_irel_data.orR || block_vol_ignt)