Merge pull request #1123 from freechipsproject/dts-global

DTS global

src/main/scala/coreplex/BaseCoreplex.scala

@@ -54,46 +54,22 @@ abstract class BaseCoreplex(implicit p: Parameters) extends BareCoreplex
     with HasMemoryBus {
   override val module: BaseCoreplexModule[BaseCoreplex]
 
-  val root = new Device {
-    def describe(resources: ResourceBindings): Description = {
-      val width = resources("width").map(_.value)
-      Description("/", Map(
-        "#address-cells" -> width,
-        "#size-cells"    -> width,
-        "model"          -> Seq(ResourceString(p(DTSModel))),
-        "compatible"     -> (p(DTSModel) +: p(DTSCompat)).map(s => ResourceString(s + "-dev"))))
-    }
-  }
-
-  val soc = new Device {
-    def describe(resources: ResourceBindings): Description = {
-      val width = resources("width").map(_.value)
-      Description("soc", Map(
-        "#address-cells" -> width,
-        "#size-cells"    -> width,
-        "compatible"     -> ((p(DTSModel) +: p(DTSCompat)).map(s => ResourceString(s + "-soc")) :+ ResourceString("simple-bus")),
-        "ranges"         -> Nil))
-    }
-  }
-
-  val cpus = new Device {
-    def describe(resources: ResourceBindings): Description = {
-      Description("cpus", Map(
-        "#address-cells"     -> Seq(ResourceInt(1)),
-        "#size-cells"        -> Seq(ResourceInt(0)),
-        "timebase-frequency" -> Seq(ResourceInt(p(DTSTimebase)))))
-    }
-  }
-
   // Make topManagers an Option[] so as to avoid LM name reflection evaluating it...
   lazy val topManagers = Some(ManagerUnification(sharedMemoryTLEdge.manager.managers))
   ResourceBinding {
     val managers = topManagers.get
     val max = managers.flatMap(_.address).map(_.max).max
     val width = ResourceInt((log2Ceil(max)+31) / 32)
-    Resource(root, "width").bind(width)
-    Resource(soc,  "width").bind(width)
-    Resource(cpus, "null").bind(ResourceString(""))
+    val model = p(DTSModel)
+    val compat = p(DTSCompat)
+    val devCompat = (model +: compat).map(s => ResourceString(s + "-dev"))
+    val socCompat = (model +: compat).map(s => ResourceString(s + "-soc"))
+    devCompat.foreach { Resource(ResourceAnchors.root, "compat").bind(_) }
+    socCompat.foreach { Resource(ResourceAnchors.soc,  "compat").bind(_) }
+    Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
+    Resource(ResourceAnchors.root, "width").bind(width)
+    Resource(ResourceAnchors.soc,  "width").bind(width)
+    Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
 
     managers.foreach { case manager =>
       val value = manager.toResource

src/main/scala/diplomacy/Resources.scala

@@ -256,7 +256,7 @@ trait BindingScope
     eval
     val map: Map[Device, ResourceBindings] =
       resourceBindings.reverse.groupBy(_._1.owner).mapValues(seq => ResourceBindings(
-        seq.groupBy(_._1.key).mapValues(_.map(z => Binding(z._2, z._3)))))
+        seq.groupBy(_._1.key).mapValues(_.map(z => Binding(z._2, z._3)).distinct)))
     val tree = makeTree(map.toList.flatMap { case (d, m) =>
       val Description(name, mapping) = d.describe(m)
       val tokens = name.split("/").toList
@@ -269,7 +269,7 @@ object BindingScope
 {
   protected[diplomacy] var active: Option[BindingScope] = None
   protected[diplomacy] def find(m: Option[LazyModule] = LazyModule.scope): Option[BindingScope] = m.flatMap {
-    case s: BindingScope => Some(s)
+    case x: BindingScope => find(x.parent).orElse(Some(x))
     case x => find(x.parent)
   }
 }
@@ -285,3 +285,40 @@ object ResourceBinding
     scope.get.resourceBindingFns = { () => block } +: scope.get.resourceBindingFns
   }
 }
+
+object ResourceAnchors
+{
+  val root = new Device {
+    def describe(resources: ResourceBindings): Description = {
+      val width = resources("width").map(_.value)
+      val model = resources("model").map(_.value)
+      val compat = resources("compat").map(_.value)
+      Description("/", Map(
+        "#address-cells" -> width,
+        "#size-cells"    -> width,
+        "model"          -> model,
+        "compatible"     -> compat))
+    }
+  }
+
+  val soc = new Device {
+    def describe(resources: ResourceBindings): Description = {
+      val width = resources("width").map(_.value)
+      val compat = resources("compat").map(_.value) :+ ResourceString("simple-bus")
+      Description("soc", Map(
+        "#address-cells" -> width,
+        "#size-cells"    -> width,
+        "compatible"     -> compat,
+        "ranges"         -> Nil))
+    }
+  }
+
+  val cpus = new Device {
+    def describe(resources: ResourceBindings): Description = {
+      val width = resources("width").map(_.value)
+      Description("cpus", Map(
+        "#address-cells" -> width,
+        "#size-cells"    -> Seq(ResourceInt(0))))
+    }
+  }
+}

src/main/scala/tile/RocketTile.scala

@@ -66,6 +66,9 @@ class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) ext
       val itim = if (frontend.icache.slaveNode.edges.in.isEmpty) Map() else Map(
         "sifive,itim"          -> ofRef(frontend.icache.device))
 
+      val incoherent = if (!rocketParams.core.useAtomicsOnlyForIO) Map() else Map(
+        "sifive,d-cache-incoherent" -> Nil)
+
       val icache = rocketParams.icache.map(i => Map(
         "i-cache-block-size"   -> ofInt(block),
         "i-cache-sets"         -> ofInt(i.nSets),
@@ -104,8 +107,8 @@ class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) ext
         "compatible"           -> Seq(ResourceString("sifive,rocket0"), ResourceString("riscv")),
         "status"               -> ofStr("okay"),
         "clock-frequency"      -> Seq(ResourceInt(rocketParams.core.bootFreqHz)),
-        "riscv,isa"            -> ofStr(isa))
-        ++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb ++ dtim ++itim)
+        "riscv,isa"            -> ofStr(isa),
+        "timebase-frequency"   -> Seq(ResourceInt(p(DTSTimebase)))) ++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb ++ dtim ++ itim ++ incoherent)
     }
   }
   val intcDevice = new Device {