riscv/rocket-chip
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Automatically infer rocketCAM address width

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This commit is contained in:
Andrew Waterman 2011-12-05 15:45:44 -08:00
parent fa784d1d7d
commit a87ad06780
2 changed files with 6 additions and 5 deletions
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2
rocket/src/main/scala/dtlb.scala
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@ -68,7 +68,7 @@ class rocketDTLB(entries: Int) extends Component
val lookup_tag = Cat(r_cpu_req_asid, r_cpu_req_vpn); val lookup_tag = Cat(r_cpu_req_asid, r_cpu_req_vpn);
val tag_cam = new rocketCAM(entries, addr_bits, ASID_BITS+VPN_BITS); val tag_cam = new rocketCAM(entries, ASID_BITS+VPN_BITS);
val tag_ram = Mem(entries, io.ptw.resp_val, r_refill_waddr.toUFix, io.ptw.resp_ppn); val tag_ram = Mem(entries, io.ptw.resp_val, r_refill_waddr.toUFix, io.ptw.resp_ppn);
tag_cam.io.clear := io.cpu.invalidate; tag_cam.io.clear := io.cpu.invalidate;

5
rocket/src/main/scala/itlb.scala
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@ -18,7 +18,8 @@ class ioCAM(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle {
val write_addr = UFix(addr_bits, 'input); val write_addr = UFix(addr_bits, 'input);
} }
class rocketCAM(entries: Int, addr_bits: Int, tag_bits: Int) extends Component { class rocketCAM(entries: Int, tag_bits: Int) extends Component {
val addr_bits = ceil(log(entries)/log(2)).toInt;
val io = new ioCAM(entries, addr_bits, tag_bits); val io = new ioCAM(entries, addr_bits, tag_bits);
val cam_tags = Mem(entries, io.write, io.write_addr, io.write_tag); val cam_tags = Mem(entries, io.write, io.write_addr, io.write_tag);
@ -112,7 +113,7 @@ class rocketITLB(entries: Int) extends Component
val lookup_tag = Cat(r_cpu_req_asid, r_cpu_req_vpn); val lookup_tag = Cat(r_cpu_req_asid, r_cpu_req_vpn);
val tag_cam = new rocketCAM(entries, addr_bits, ASID_BITS+VPN_BITS); val tag_cam = new rocketCAM(entries, ASID_BITS+VPN_BITS);
val tag_ram = Mem(entries, io.ptw.resp_val, r_refill_waddr.toUFix, io.ptw.resp_ppn); val tag_ram = Mem(entries, io.ptw.resp_val, r_refill_waddr.toUFix, io.ptw.resp_ppn);
tag_cam.io.clear := io.cpu.invalidate; tag_cam.io.clear := io.cpu.invalidate;