riscv/rocket-chip
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Yunsup Lee 2013-05-01 02:58:53 -07:00
parent 50bd9a08a7
commit a86ad08c1e
2 changed files with 18 additions and 16 deletions
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10
Makefrag
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@ -6,17 +6,17 @@ CXXFLAGS := -O2
SBT := java -Xmx2048M -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar SBT := java -Xmx2048M -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar
DRAMSIM_OBJS := $(patsubst %.cpp,%.o,$(wildcard $(basedir)/dramsim2/*.cpp)) DRAMSIM_OBJS := $(patsubst %.cpp,%.o,$(wildcard $(base_dir)/dramsim2/*.cpp))
$(DRAMSIM_OBJS): %.o: %.cpp $(DRAMSIM_OBJS): %.o: %.cpp
$(CXX) $(CXXFLAGS) -DNO_STORAGE -DNO_OUTPUT -Dmain=nomain -c -o $@ $< $(CXX) $(CXXFLAGS) -DNO_STORAGE -DNO_OUTPUT -Dmain=nomain -c -o $@ $<
libdramsim.a: $(DRAMSIM_OBJS) $(sim_dir)/libdramsim.a: $(DRAMSIM_OBJS)
ar rcs $@ $^ ar rcs $@ $^
#-------------------------------------------------------------------- #--------------------------------------------------------------------
# Tests # Tests
#-------------------------------------------------------------------- #--------------------------------------------------------------------
tstdir = $(basedir)/riscv-tests/isa tstdir = $(base_dir)/riscv-tests/isa
asm_p_tests = \ asm_p_tests = \
rv64si-pm-ipi \ rv64si-pm-ipi \
rv64ui-pm-lrsc \ rv64ui-pm-lrsc \
@ -491,7 +491,7 @@ vecasm_pt_tests = \
# Globally installed benchmarks # Globally installed benchmarks
bmarkdir = $(basedir)/riscv-tests/benchmarks bmarkdir = $(base_dir)/riscv-tests/benchmarks
bmarks = \ bmarks = \
median.riscv \ median.riscv \
multiply.riscv \ multiply.riscv \
@ -507,7 +507,7 @@ bmarks = \
mt-vvadd.riscv \ mt-vvadd.riscv \
mt-matmul.riscv \ mt-matmul.riscv \
vec_bmarkdir = $(basedir)/../../riscv-app/misc/build vec_bmarkdir = $(base_dir)/../../riscv-app/misc/build
vec_bmarks = \ vec_bmarks = \
ubmark-vvadd \ ubmark-vvadd \
ubmark-bin-search \ ubmark-bin-search \

24
emulator/Makefile
View File

@ -1,26 +1,28 @@
all: emulator all: emulator
basedir = .. base_dir = ..
include ../Makefrag sim_dir = .
include $(base_dir)/Makefrag
CXXFLAGS := $(CXXFLAGS) -std=c++0x -I$(RISCV)/include CXXFLAGS := $(CXXFLAGS) -std=c++0x -I$(RISCV)/include
CXXSRCS := emulator disasm mm mm_dramsim2 CXXSRCS := emulator disasm mm mm_dramsim2
CXXFLAGS := $(CXXFLAGS) -I$(basedir)/csrc -I$(basedir)/chisel/csrc -I$(basedir)/dramsim2 CXXFLAGS := $(CXXFLAGS) -I$(base_dir)/csrc -I$(base_dir)/chisel/csrc -I$(base_dir)/dramsim2
LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -L. -ldramsim -lfesvr -lpthread LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -L. -ldramsim -lfesvr -lpthread
OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL)) OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL))
DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL)) DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir $(basedir)/emulator/generated-src CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir $(base_dir)/emulator/generated-src
CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd --ioDebug CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd --ioDebug
generated-src/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala $(basedir)/src/*.scala generated-src/$(MODEL).cpp: $(base_dir)/riscv-rocket/src/*.scala $(base_dir)/riscv-hwacha/src/*.scala $(base_dir)/chisel/src/main/scala/* $(base_dir)/uncore/src/*.scala $(base_dir)/src/*.scala
cd $(basedir)/sbt && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS)" cd $(base_dir)/sbt && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS)"
generated-src-debug/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala $(basedir)/src/*.scala generated-src-debug/$(MODEL).cpp: $(base_dir)/riscv-rocket/src/*.scala $(base_dir)/riscv-hwacha/src/*.scala $(base_dir)/chisel/src/main/scala/* $(base_dir)/uncore/src/*.scala $(base_dir)/src/*.scala
cd $(basedir)/sbt && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS_DEBUG)" cd $(base_dir)/sbt && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS_DEBUG)"
$(MODEL).o: %.o: generated-src/%.cpp $(MODEL).o: %.o: generated-src/%.cpp
$(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $< $(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $<
@ -28,10 +30,10 @@ $(MODEL).o: %.o: generated-src/%.cpp
$(MODEL)-debug.o: %-debug.o: generated-src-debug/%.cpp $(MODEL)-debug.o: %-debug.o: generated-src-debug/%.cpp
$(CXX) $(CXXFLAGS) -Igenerated-src-debug -c -o $@ $< $(CXX) $(CXXFLAGS) -Igenerated-src-debug -c -o $@ $<
$(addsuffix .o,$(CXXSRCS)): %.o: $(basedir)/csrc/%.cc $(basedir)/csrc/*.h generated-src/$(MODEL).cpp $(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h generated-src/$(MODEL).cpp
$(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $< $(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $<
$(addsuffix -debug.o,$(CXXSRCS)): %-debug.o: $(basedir)/csrc/%.cc $(basedir)/csrc/*.h generated-src-debug/$(MODEL).cpp $(addsuffix -debug.o,$(CXXSRCS)): %-debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h generated-src-debug/$(MODEL).cpp
$(CXX) $(CXXFLAGS) -Igenerated-src-debug -c -o $@ $< $(CXX) $(CXXFLAGS) -Igenerated-src-debug -c -o $@ $<
emulator: $(OBJS) libdramsim.a emulator: $(OBJS) libdramsim.a
@ -44,7 +46,7 @@ clean:
rm -rf *.o *.a emulator emulator-debug generated-src generated-src-debug DVEfiles output rm -rf *.o *.a emulator emulator-debug generated-src generated-src-debug DVEfiles output
test: test:
cd $(basedir)/sbt && $(SBT) "project referencechip" "~make $(CURDIR) run-fast $(CHISEL_ARGS)" cd $(base_dir)/sbt && $(SBT) "project referencechip" "~make $(CURDIR) run-fast $(CHISEL_ARGS)"
#-------------------------------------------------------------------- #--------------------------------------------------------------------
# Run assembly tests and benchmarks # Run assembly tests and benchmarks