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tilelink2: replace addr_hi with address (#397)

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When faced with ambiguous routing of wmask=0, we decided to include
all the address bits. Hopefully in most cases the low bits will be
optimized away anyway.
This commit is contained in:
Wesley W. Terpstra
2016-10-14 14:09:39 -07:00
committed by Henry Cook
parent 9655621aa8
commit a82cfb8306
11 changed files with 103 additions and 175 deletions
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2
src/main/scala/uncore/tilelink2/RegisterRouter.scala
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@ -36,7 +36,7 @@ class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int =
val params = RegMapperParams(log2Up((address.mask+1)/beatBytes), beatBytes, addrLoEnd)
val in = Wire(Decoupled(new RegMapperInput(params)))
in.bits.read := a.bits.opcode === TLMessages.Get
in.bits.index := a.bits.addr_hi
in.bits.index := edge.addr_hi(a.bits)
in.bits.data := a.bits.data
in.bits.mask := a.bits.mask
in.bits.extra := Cat(edge.addr_lo(a.bits), a.bits.source, a.bits.size)