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tilelink2: replace addr_hi with address (#397)

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When faced with ambiguous routing of wmask=0, we decided to include
all the address bits. Hopefully in most cases the low bits will be
optimized away anyway.
This commit is contained in:
Wesley W. Terpstra
2016-10-14 14:09:39 -07:00
committed by Henry Cook
parent 9655621aa8
commit a82cfb8306
11 changed files with 103 additions and 175 deletions
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7
src/main/scala/uncore/tilelink2/Bundles.scala
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@ -103,7 +103,7 @@ final class TLBundleA(params: TLBundleParameters)
val param = UInt(width = 3) // amo_opcode || perms || hint
val size = UInt(width = params.sizeBits)
val source = UInt(width = params.sourceBits) // from
val addr_hi = UInt(width = params.addrHiBits) // to
val address = UInt(width = params.addressBits) // to
// variable fields during multibeat:
val mask = UInt(width = params.dataBits/8)
val data = UInt(width = params.dataBits)
@ -118,7 +118,7 @@ final class TLBundleB(params: TLBundleParameters)
val param = UInt(width = 3)
val size = UInt(width = params.sizeBits)
val source = UInt(width = params.sourceBits) // to
val addr_hi = UInt(width = params.addrHiBits) // from
val address = UInt(width = params.addressBits) // from
// variable fields during multibeat:
val mask = UInt(width = params.dataBits/8)
val data = UInt(width = params.dataBits)
@ -133,8 +133,7 @@ final class TLBundleC(params: TLBundleParameters)
val param = UInt(width = 3)
val size = UInt(width = params.sizeBits)
val source = UInt(width = params.sourceBits) // from
val addr_hi = UInt(width = params.addrHiBits) // to
val addr_lo = UInt(width = params.addrLoBits) // instead of mask
val address = UInt(width = params.addressBits) // to
// variable fields during multibeat:
val data = UInt(width = params.dataBits)
val error = Bool() // AccessAck[Data]