From a7f79aa409ca701a5f4f0dd62a2b5d47fd2a8122 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Sat, 3 Sep 2016 21:14:04 -0700
Subject: [PATCH] get rid of TileLinkMemorySelector

---
 .../scala/uncore/tilelink/Interconnect.scala  | 73 -------------------
 1 file changed, 73 deletions(-)

diff --git a/src/main/scala/uncore/tilelink/Interconnect.scala b/src/main/scala/uncore/tilelink/Interconnect.scala
index 7e3aaaaf..8a2de1b7 100644
--- a/src/main/scala/uncore/tilelink/Interconnect.scala
+++ b/src/main/scala/uncore/tilelink/Interconnect.scala
@@ -311,76 +311,3 @@ class TileLinkMemoryInterconnect(
     connectChannel(io.out(i), channelArb.io.out)
   }
 }
-
-/** Allows users to switch between various memory configurations.  Note that
-  * this is a dangerous operation: not only does switching the select input to
-  * this module violate TileLink, it also causes the memory of the machine to
-  * become garbled.  It's expected that select only changes at boot time, as
-  * part of the memory controller configuration. */
-class TileLinkMemorySelectorIO(val nBanks: Int, val maxMemChannels: Int, nConfigs: Int)
-                           (implicit p: Parameters)
-                           extends TileLinkInterconnectIO(nBanks, maxMemChannels) {
-  val select  = UInt(INPUT, width = log2Up(nConfigs))
-  override def cloneType =
-    new TileLinkMemorySelectorIO(nBanks, maxMemChannels, nConfigs).asInstanceOf[this.type]
-}
-
-class TileLinkMemorySelector(nBanks: Int, maxMemChannels: Int, configs: Seq[Int])
-                         (implicit p: Parameters)
-                         extends TileLinkInterconnect()(p) {
-  val nInner = nBanks
-  val nOuter = maxMemChannels
-  val nConfigs = configs.size
-
-  override lazy val io = new TileLinkMemorySelectorIO(nBanks, maxMemChannels, nConfigs)
-
-  def muxOnSelect[T <: Data](up: DecoupledIO[T], dn: DecoupledIO[T], active: Bool): Unit = {
-    when (active) { dn.bits  := up.bits  }
-    when (active) { up.ready := dn.ready }
-    when (active) { dn.valid := up.valid }
-  }
-
-  def muxOnSelect(up: ClientUncachedTileLinkIO, dn: ClientUncachedTileLinkIO, active: Bool): Unit = {
-    muxOnSelect(up.acquire, dn.acquire, active)
-    muxOnSelect(dn.grant, up.grant, active)
-  }
-
-  def muxOnSelect(up: Vec[ClientUncachedTileLinkIO], dn: Vec[ClientUncachedTileLinkIO], active: Bool) : Unit = {
-    for (i <- 0 until up.size)
-      muxOnSelect(up(i), dn(i), active)
-  }
-
-  /* Disconnects a vector of TileLink ports, which involves setting them to
-   * invalid.  Due to Chisel reasons, we need to also set the bits to 0 (since
-   * there can't be any unconnected inputs). */
-  def disconnectOuter(outer: Vec[ClientUncachedTileLinkIO]) = {
-    outer.foreach{ m =>
-      m.acquire.valid := Bool(false)
-      m.acquire.bits := m.acquire.bits.fromBits(UInt(0))
-      m.grant.ready := Bool(false)
-    }
-  }
-
-  def disconnectInner(inner: Vec[ClientUncachedTileLinkIO]) = {
-    inner.foreach { m =>
-      m.grant.valid := Bool(false)
-      m.grant.bits := m.grant.bits.fromBits(UInt(0))
-      m.acquire.ready := Bool(false)
-    }
-  }
-
-  /* Provides default wires on all our outputs. */
-  disconnectOuter(io.out)
-  disconnectInner(io.in)
-
-  /* Constructs interconnects for each of the layouts suggested by the
-   * configuration and switches between them based on the select input. */
-  configs.zipWithIndex.foreach{ case (nChannels, select) =>
-    val nBanksPerChannel = nBanks / nChannels
-    val ic = Module(new TileLinkMemoryInterconnect(nBanksPerChannel, nChannels))
-    disconnectInner(ic.io.out)
-    disconnectOuter(ic.io.in)
-    muxOnSelect(io.in, ic.io.in, io.select === UInt(select))
-    muxOnSelect(ic.io.out, io.out, io.select === UInt(select))
-  }
-}