riscv/rocket-chip
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rocketchip: fix all clock crossings

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This commit is contained in:
Wesley W. Terpstra
2016-10-27 15:34:37 -07:00
parent 825c253a72
commit a73aa351ca
6 changed files with 89 additions and 41 deletions
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5
src/main/scala/rocketchip/ExampleTop.scala
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@ -15,7 +15,8 @@ class ExampleTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit p:
with PeripheryExtInterrupts
with PeripheryMasterMem
with PeripheryMasterAXI4MMIO
with PeripherySlave {
with PeripherySlave
with DirectConnection {
override lazy val module = new ExampleTopModule(this, new ExampleTopBundle(this))
}
@ -35,7 +36,7 @@ class ExampleTopModule[+L <: ExampleTop[BaseCoreplex], +B <: ExampleTopBundle[L]
with PeripheryMasterAXI4MMIOModule
with PeripherySlaveModule
with HardwiredResetVector
with DirectConnection
with DirectConnectionModule
/** Example Top with TestRAM */
class ExampleTopWithTestRAM[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(buildCoreplex)