riscv/rocket-chip
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rocketchip: fix all clock crossings

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This commit is contained in:
Wesley W. Terpstra
2016-10-27 15:34:37 -07:00
parent 825c253a72
commit a73aa351ca
6 changed files with 89 additions and 41 deletions
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28
src/main/scala/rocketchip/BaseTop.scala
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@ -54,8 +54,6 @@ abstract class BaseTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(impli
TLWidthWidget(p(SOCBusKey).beatBytes)(
socBus.node)))
socBus.node := coreplex.mmio
TopModule.contents = Some(this)
}
@ -66,7 +64,11 @@ abstract class BaseTopBundle[+L <: BaseTop[BaseCoreplex]](val outer: L) extends
abstract class BaseTopModule[+L <: BaseTop[BaseCoreplex], +B <: BaseTopBundle[L]](val outer: L, val io: B) extends LazyModuleImp(outer) {
implicit val p = outer.p
val coreplexIO = Wire(outer.coreplex.module.io)
val coreplexMem : Vec[ClientUncachedTileLinkIO] = Wire(outer.coreplex.module.io.mem)
val coreplexSlave : Vec[ClientUncachedTileLinkIO] = Wire(outer.coreplex.module.io.slave)
val coreplexDebug : DebugBusIO = Wire(outer.coreplex.module.io.debug)
val coreplexInterrupts : Vec[Bool] = Wire(outer.coreplex.module.io.interrupts)
println("Generated Address Map")
for (entry <- p(GlobalAddrMap).flatten) {
@ -88,12 +90,26 @@ abstract class BaseTopModule[+L <: BaseTop[BaseCoreplex], +B <: BaseTopBundle[L]
println(p(ConfigString))
ConfigStringOutput.contents = Some(p(ConfigString))
io.success := coreplexIO.success
io.success := outer.coreplex.module.io.success
}
trait DirectConnection {
val coreplexIO: BaseCoreplexBundle[BaseCoreplex]
val coreplex: BaseCoreplex
val socBus: TLXbar
socBus.node := coreplex.mmio
}
trait DirectConnectionModule {
val outer: BaseTop[BaseCoreplex]
coreplexIO <> outer.coreplex.module.io
val coreplexMem : Vec[ClientUncachedTileLinkIO]
val coreplexSlave : Vec[ClientUncachedTileLinkIO]
val coreplexDebug : DebugBusIO
val coreplexInterrupts : Vec[Bool]
coreplexMem <> outer.coreplex.module.io.mem
coreplexInterrupts <> outer.coreplex.module.io.interrupts
outer.coreplex.module.io.slave <> coreplexSlave
outer.coreplex.module.io.debug <> coreplexDebug
}

5
src/main/scala/rocketchip/ExampleTop.scala
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@ -15,7 +15,8 @@ class ExampleTop[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit p:
with PeripheryExtInterrupts
with PeripheryMasterMem
with PeripheryMasterAXI4MMIO
with PeripherySlave {
with PeripherySlave
with DirectConnection {
override lazy val module = new ExampleTopModule(this, new ExampleTopBundle(this))
}
@ -35,7 +36,7 @@ class ExampleTopModule[+L <: ExampleTop[BaseCoreplex], +B <: ExampleTopBundle[L]
with PeripheryMasterAXI4MMIOModule
with PeripherySlaveModule
with HardwiredResetVector
with DirectConnection
with DirectConnectionModule
/** Example Top with TestRAM */
class ExampleTopWithTestRAM[+C <: BaseCoreplex](buildCoreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(buildCoreplex)

23
src/main/scala/rocketchip/Periphery.scala
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@ -110,16 +110,16 @@ trait PeripheryDebugModule {
implicit val p: Parameters
val outer: PeripheryDebug
val io: PeripheryDebugBundle
val coreplexIO: BaseCoreplexBundle[BaseCoreplex]
val coreplexDebug: DebugBusIO
if (p(IncludeJtagDTM)) {
// JtagDTMWithSync is a wrapper which
// handles the synchronization as well.
val dtm = Module (new JtagDTMWithSync()(p))
dtm.io.jtag <> io.jtag.get
coreplexIO.debug <> dtm.io.debug
coreplexDebug <> dtm.io.debug
} else {
coreplexIO.debug <>
coreplexDebug <>
(if (p(AsyncDebugBus)) AsyncDebugBusFrom(io.debug_clk.get, io.debug_rst.get, io.debug.get)
else io.debug.get)
}
@ -143,12 +143,12 @@ trait PeripheryExtInterruptsModule {
implicit val p: Parameters
val outer: PeripheryExtInterrupts
val io: PeripheryExtInterruptsBundle
val coreplexIO: BaseCoreplexBundle[BaseCoreplex]
val coreplexInterrupts: Vec[Bool]
{
val r = outer.pInterrupts.range("ext")
((r._1 until r._2) zipWithIndex) foreach { case (c, i) =>
coreplexIO.interrupts(c) := io.interrupts(i)
coreplexInterrupts(c) := io.interrupts(i)
}
}
}
@ -172,9 +172,9 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
implicit val p: Parameters
val outer: PeripheryMasterMem
val io: PeripheryMasterMemBundle
val coreplexIO: BaseCoreplexBundle[BaseCoreplex]
val coreplexMem: Vec[ClientUncachedTileLinkIO]
val edgeMem = coreplexIO.master.mem.map(TileLinkWidthAdapter(_, edgeMemParams))
val edgeMem = coreplexMem.map(TileLinkWidthAdapter(_, edgeMemParams))
// Abuse the fact that zip takes the shorter of the two lists
((io.mem_axi zip edgeMem) zipWithIndex) foreach { case ((axi, mem), idx) =>
@ -254,7 +254,7 @@ trait PeripherySlaveModule extends HasPeripheryParameters {
implicit val p: Parameters
val outer: PeripherySlave
val io: PeripherySlaveBundle
val coreplexIO: BaseCoreplexBundle[BaseCoreplex]
val coreplexSlave: Vec[ClientUncachedTileLinkIO]
if (p(NExtBusAXIChannels) > 0) {
val arb = Module(new NastiArbiter(p(NExtBusAXIChannels)))
@ -269,7 +269,7 @@ trait PeripherySlaveModule extends HasPeripheryParameters {
val (r_start, r_end) = outer.pBusMasters.range("ext")
require(r_end - r_start == 1, "RangeManager should return 1 slot")
TileLinkWidthAdapter(coreplexIO.slave(r_start), conv.io.tl)
TileLinkWidthAdapter(coreplexSlave(r_start), conv.io.tl)
}
}
@ -340,6 +340,7 @@ trait PeripheryTestBusMasterModule {
/////
trait HardwiredResetVector {
val coreplexIO: BaseCoreplexBundle[BaseCoreplex]
coreplexIO.resetVector := UInt(0x1000) // boot ROM
val outer: BaseTop[BaseCoreplex]
outer.coreplex.module.io.resetVector := UInt(0x1000) // boot ROM
}