riscv/rocket-chip
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rocketchip: fix all clock crossings

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This commit is contained in:
Wesley W. Terpstra
2016-10-27 15:34:37 -07:00
parent 825c253a72
commit a73aa351ca
6 changed files with 89 additions and 41 deletions
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5
src/main/scala/groundtest/Coreplex.scala
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@ -4,13 +4,14 @@ import Chisel._
import cde.{Parameters}
import coreplex._
class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
with DirectConnection {
override lazy val module = new GroundTestCoreplexModule(this, new GroundTestCoreplexBundle(this))
}
class GroundTestCoreplexBundle[+L <: GroundTestCoreplex](outer: L) extends BaseCoreplexBundle(outer)
class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io)
with DirectConnection {
with DirectConnectionModule {
io.success := tiles.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
}