riscv/rocket-chip
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rocketchip: fix all clock crossings

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This commit is contained in:
Wesley W. Terpstra
2016-10-27 15:34:37 -07:00
parent 825c253a72
commit a73aa351ca
6 changed files with 89 additions and 41 deletions
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16
src/main/scala/coreplex/BaseCoreplex.scala
View File

@ -68,16 +68,11 @@ abstract class BareCoreplex(implicit val p: Parameters) extends LazyModule with
abstract class BareCoreplexBundle[+L <: BareCoreplex](val outer: L) extends Bundle with HasCoreplexParameters {
implicit val p = outer.p
val master = new Bundle {
val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outerMemParams))
val mmio = outer.mmio.bundleOut
}
val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outerMemParams))
val mmio = outer.mmio.bundleOut
val slave = Vec(nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
val resetVector = UInt(INPUT, p(XLen))
val success = Bool(OUTPUT) // used for testing
override def cloneType = this.getClass.getConstructors.head.newInstance(outer).asInstanceOf[this.type]
}
abstract class BareCoreplexModule[+L <: BareCoreplex, +B <: BareCoreplexBundle[L]](val outer: L, val io: B) extends LazyModuleImp(outer) with HasCoreplexParameters {
@ -134,7 +129,7 @@ abstract class BareCoreplexModule[+L <: BareCoreplex, +B <: BareCoreplexBundle[L
icPort <> TileLinkIOUnwrapper(enqueued)
}
io.master.mem <> mem_ic.io.out
io.mem <> mem_ic.io.out
}
for ((tile, i) <- (uncoreTileIOs zipWithIndex)) {
@ -150,7 +145,6 @@ trait CoreplexPeripherals extends HasCoreplexParameters {
val module: CoreplexPeripheralsModule
val l1tol2: TLXbar
val legacy: TLLegacy
val lazyTiles: Seq[LazyTile]
val cbus = LazyModule(new TLXbar)
val debug = LazyModule(new TLDebugModule())
@ -166,10 +160,6 @@ trait CoreplexPeripherals extends HasCoreplexParameters {
debug.node := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
plic.node := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
clint.node := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
lazyTiles.map(_.slave).flatten.foreach { scratch =>
scratch := TLFragmenter(p(XLen)/8, legacy.tlDataBeats * legacy.tlDataBytes)(cbus.node)
}
}
trait CoreplexPeripheralsBundle extends HasCoreplexParameters {

53
src/main/scala/coreplex/Coreplex.scala
View File

@ -3,12 +3,23 @@ package coreplex
import Chisel._
import cde.{Parameters, Field}
import junctions._
import diplomacy._
import uncore.tilelink._
import uncore.tilelink2._
import uncore.util._
import util._
import rocket._
trait DirectConnection {
implicit val p: Parameters
val lazyTiles: Seq[LazyTile]
val legacy: TLLegacy
val cbus: TLXbar
lazyTiles.map(_.slave).flatten.foreach { scratch => scratch := cbus.node }
}
trait DirectConnectionModule {
val tiles: Seq[TileImp]
val uncoreTileIOs: Seq[TileIO]
@ -18,7 +29,6 @@ trait DirectConnection {
(tiles zip uncoreTileIOs) foreach { case (tile, uncore) =>
(uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, tlBuffering) }
(uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, ultBuffering) }
// !!! tile.io.slave.foreach { _ <> TileLinkEnqueuer(uncore.slave.get, 1) }
tile.io.interrupts <> uncore.interrupts
@ -27,18 +37,19 @@ trait DirectConnection {
}
}
class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex {
class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex
with DirectConnection {
override lazy val module = new DefaultCoreplexModule(this, new DefaultCoreplexBundle(this))
}
class DefaultCoreplexBundle[+L <: DefaultCoreplex](outer: L) extends BaseCoreplexBundle(outer)
class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io)
with DirectConnection
with DirectConnectionModule
/////
trait TileClockResetBundle extends HasCoreplexParameters {
trait TileClockResetBundle extends Bundle with HasCoreplexParameters {
val tcrs = Vec(nTiles, new Bundle {
val clock = Clock(INPUT)
val reset = Bool(INPUT)
@ -46,9 +57,37 @@ trait TileClockResetBundle extends HasCoreplexParameters {
}
trait AsyncConnection {
implicit val p: Parameters
val lazyTiles: Seq[LazyTile]
val legacy: TLLegacy
val cbus: TLXbar
val crossings = lazyTiles.map(_.slave).map(_.map { scratch =>
val crossing = LazyModule(new TLAsyncCrossing)
crossing.node := cbus.node
val monitor = (scratch := crossing.node)
(crossing, monitor)
})
}
trait AsyncConnectionModule extends Module {
val io: TileClockResetBundle
val tiles: Seq[TileImp]
val uncoreTileIOs: Seq[TileIO]
val outer: AsyncConnection
(outer.crossings zip io.tcrs) foreach { case (slaves, tcr) =>
slaves.foreach { case (crossing, monitor) =>
crossing.module.io.in_clock := clock
crossing.module.io.in_reset := reset
crossing.module.io.out_clock := tcr.clock
crossing.module.io.out_reset := tcr.reset
monitor.foreach { m =>
m.module.clock := tcr.clock
m.module.reset := tcr.reset
}
}
}
(tiles, uncoreTileIOs, io.tcrs).zipped foreach { case (tile, uncore, tcr) =>
tile.clock := tcr.clock
@ -56,7 +95,6 @@ trait AsyncConnection {
(uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> AsyncTileLinkFrom(tcr.clock, tcr.reset, t) }
(uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> AsyncUTileLinkFrom(tcr.clock, tcr.reset, t) }
// !!! tile.io.slave.foreach { _ <> AsyncUTileLinkTo(tcr.clock, tcr.reset, uncore.slave.get)}
val ti = tile.io.interrupts
val ui = uncore.interrupts
@ -71,7 +109,8 @@ trait AsyncConnection {
}
}
class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex {
class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex
with AsyncConnection {
override lazy val module = new MultiClockCoreplexModule(this, new MultiClockCoreplexBundle(this))
}
@ -79,4 +118,4 @@ class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](outer: L) extends BaseC
with TileClockResetBundle
class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](outer: L, io: B) extends BaseCoreplexModule(outer, io)
with AsyncConnection
with AsyncConnectionModule