Update history register in fetch speculatively
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f917810061
commit
a71bdbbc54
@ -41,7 +41,9 @@ class RAS(nras: Int) {
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}
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}
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class BHTResp extends Bundle with BTBParameters {
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class BHTResp extends Bundle with BTBParameters {
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// TODO only carry history, not both index and history
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val index = UInt(width = log2Up(nBHT).max(1))
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val index = UInt(width = log2Up(nBHT).max(1))
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val history = UInt(width = log2Up(nBHT).max(1))
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val value = UInt(width = 2)
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val value = UInt(width = 2)
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}
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}
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@ -50,12 +52,19 @@ class BHT(nbht: Int) {
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def get(addr: UInt): BHTResp = {
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def get(addr: UInt): BHTResp = {
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val res = new BHTResp
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val res = new BHTResp
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res.index := addr(nbhtbits+1,2) ^ history
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res.index := addr(nbhtbits+1,2) ^ history
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res.history := history
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res.value := table(res.index)
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res.value := table(res.index)
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// TODO we actually want to include the final prediction result from the BTB
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val taken = res.value(0)
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// TODO only update history on an actual instruction fetch
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history := Cat(taken, history(nbhtbits-1,1))
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res
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res
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}
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}
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def update(d: BHTResp, taken: Bool): Unit = {
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def update(d: BHTResp, taken: Bool, mispredict: Bool): Unit = {
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table(d.index) := Cat(taken, (d.value(1) & d.value(0)) | ((d.value(1) | d.value(0)) & taken))
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table(d.index) := Cat(taken, (d.value(1) & d.value(0)) | ((d.value(1) | d.value(0)) & taken))
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history := Cat(taken, history(nbhtbits-1,1))
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when (mispredict) {
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history := Cat(taken, d.history(nbhtbits-1,1))
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}
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}
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}
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private val table = Mem(UInt(width = 2), nbht)
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private val table = Mem(UInt(width = 2), nbht)
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@ -197,7 +206,7 @@ class BTB extends Module with BTBParameters {
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if (nBHT > 0) {
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if (nBHT > 0) {
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val bht = new BHT(nBHT)
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val bht = new BHT(nBHT)
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val res = bht.get(io.req)
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val res = bht.get(io.req)
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when (update.valid && updateHit && !update.bits.isJump) { bht.update(update.bits.prediction.bits.bht, update.bits.taken) }
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when (update.valid && updateHit && !update.bits.isJump) { bht.update(update.bits.prediction.bits.bht, update.bits.taken, update.bits.incorrectTarget) }
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when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false }
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when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false }
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io.resp.bits.bht := res
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io.resp.bits.bht := res
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}
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}
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