axi4: prototype Fragmenter
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Wesley W. Terpstra
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c918aa6d89
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268
src/main/scala/uncore/axi4/Fragmenter.scala
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268
src/main/scala/uncore/axi4/Fragmenter.scala
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// See LICENSE for license details.
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package uncore.axi4
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import chisel3.util.IrrevocableIO
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import diplomacy._
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import scala.math.{min,max}
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import uncore.tilelink2.{leftOR, rightOR, UIntToOH1}
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// lite: masters all use only one ID => reads will not be interleaved
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class AXI4Fragmenter(lite: Boolean = false, maxInFlight: Int = 32, combinational: Boolean = true) extends LazyModule
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{
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val maxBeats = 1 << AXI4Parameters.lenBits
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def expandTransfer(x: TransferSizes, beatBytes: Int, alignment: BigInt) =
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if (!x) x else TransferSizes(x.min, alignment.min(maxBeats*beatBytes).intValue)
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def mapSlave(s: AXI4SlaveParameters, beatBytes: Int) = s.copy(
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supportsWrite = expandTransfer(s.supportsWrite, beatBytes, s.minAlignment),
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supportsRead = expandTransfer(s.supportsRead, beatBytes, s.minAlignment),
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interleavedId = if (lite) Some(0) else s.interleavedId) // we preserve interleaving guarantees
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def mapMaster(m: AXI4MasterParameters) = m.copy(aligned = true)
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val node = AXI4AdapterNode(
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masterFn = { case Seq(mp) => mp.copy(masters = mp.masters.map(m => mapMaster(m))) },
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slaveFn = { case Seq(sp) => sp.copy(slaves = sp.slaves .map(s => mapSlave(s, sp.beatBytes))) })
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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val edgeOut = node.edgesOut(0)
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val edgeIn = node.edgesIn(0)
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val slave = edgeOut.slave
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val slaves = slave.slaves
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val beatBytes = slave.beatBytes
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val lgBytes = log2Ceil(beatBytes)
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val master = edgeIn.master
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val masters = master.masters
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// If the user claimed this was a lite interface, then there must be only one Id
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require (!lite || master.endId == 1)
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// We don't support fragmenting to sub-beat accesses
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slaves.foreach { s =>
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require (!s.supportsRead || s.supportsRead.contains(beatBytes))
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require (!s.supportsWrite || s.supportsWrite.contains(beatBytes))
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}
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/* We need to decompose a request into
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* FIXED => each beat is a new request
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* WRAP/INCR => take xfr up to next power of two, capped by max size of target
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*
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* On AR and AW, we fragment the requests
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* On W we insert 'last' to match
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* On R we surpress 'last'
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* On B we surpress 'valid'
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*
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* AR=>R and AW+W=>B are completely independent state machines.
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*/
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/* Returns the number of beats to execute and the new address */
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def fragment(a: IrrevocableIO[AXI4BundleA], supportedSizes1: Seq[Int]): (IrrevocableIO[AXI4BundleA], Bool, UInt) = {
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val out = Wire(a)
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val busy = RegInit(Bool(false))
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val r_addr = Reg(UInt(width = a.bits.params.addrBits))
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val r_len = Reg(UInt(width = AXI4Parameters.lenBits))
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val len = Mux(busy, r_len, a.bits.len)
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val addr = Mux(busy, r_addr, a.bits.addr)
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val lo = if (lgBytes == 0) UInt(0) else addr(lgBytes-1, 0)
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val hi = addr >> lgBytes
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val alignment = hi(AXI4Parameters.lenBits-1,0)
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val allSame = supportedSizes1.distinct.size == 1
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val dynamic1 = Mux1H(slave.findFast(addr), supportedSizes1.map(s => UInt(s)))
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val fixed1 = UInt(supportedSizes1(0))
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/* We need to compute the largest transfer allowed by the AXI len.
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* len+1 is the number of beats to execute.
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* We want the MSB(len+1)-1; one less than the largest power of two we could execute.
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* There are two cases; either len is 2^n-1 in which case we leave it unchanged, ELSE
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* fill the bits from highest to lowest, and shift right by one bit.
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*/
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val fillLow = rightOR(len) >> 1 // set all bits in positions < a set bit
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val wipeHigh = ~leftOR(~len) // clear all bits in position >= a cleared bit
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val remain1 = fillLow | wipeHigh // MSB(a.len+1)-1
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val align1 = ~leftOR(alignment) // transfer size limited by address alignment
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val support1 = if (allSame) fixed1 else dynamic1 // maximum supported size-1 based on target address
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val maxSupported1 = remain1 & align1 & support1 // Take the minimum of all the limits
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// Things that cause us to degenerate to a single beat
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val fixed = a.bits.burst === AXI4Parameters.BURST_FIXED
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val narrow = a.bits.size =/= UInt(lgBytes)
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val misaligned = lo =/= UInt(0)
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val bad = fixed || narrow || misaligned
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// The number of beats-1 to execute
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val beats1 = Mux(bad, UInt(0), maxSupported1)
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val beats = ~(~(beats1 << 1 | UInt(1)) | beats1) // beats1 + 1
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val inc_addr = addr + (beats << a.bits.size) // address after adding transfer
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val align_addr = ~(~inc_addr | UIntToOH1(a.bits.size, lgBytes)) // AXI4 increments misaligned heads to aligned
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val wrapMask = ~(~a.bits.len << a.bits.size) // only these bits may change, if wrapping
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val mux_addr = Wire(init = align_addr)
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when (a.bits.burst === AXI4Parameters.BURST_WRAP) {
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mux_addr := (align_addr & wrapMask) | ~(~a.bits.addr | wrapMask)
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}
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when (a.bits.burst === AXI4Parameters.BURST_FIXED) {
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mux_addr := a.bits.addr
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}
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val last = beats1 === len
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a.ready := out.ready && last
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out.valid := a.valid
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out.bits := a.bits
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out.bits.addr := addr
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out.bits.len := beats1
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when (out.fire()) {
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busy := !last
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r_addr := mux_addr
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r_len := len - beats
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}
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(out, last, beats)
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}
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val in = io.in(0)
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val out = io.out(0)
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// The size to which we will fragment the access
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val readSizes1 = slaves.map(s => s.supportsRead .max/beatBytes-1)
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val writeSizes1 = slaves.map(s => s.supportsWrite.max/beatBytes-1)
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// Indirection variables for inputs and outputs; makes transformation application easier
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val (in_ar, ar_last, _) = fragment(in.ar, readSizes1)
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val (in_aw, aw_last, w_beats) = fragment(in.aw, writeSizes1)
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val in_w = in.w
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val in_r = in.r
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val in_b = in.b
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val out_ar = Wire(out.ar)
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val out_aw = out.aw
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val out_w = out.w
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val out_r = Wire(out.r)
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val out_b = Wire(out.b)
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val depth = if (combinational) 1 else 2
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// In case a slave ties arready := rready, we need a queue to break the combinational loop
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// between the two branches (in_ar => {out_ar => out_r, sideband} => in_r).
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if (in.ar.bits.getWidth < in.r.bits.getWidth) {
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out.ar <> Queue(out_ar, depth, flow=combinational)
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out_r <> out.r
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} else {
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out.ar <> out_ar
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out_r <> Queue(out.r, depth, flow=combinational)
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}
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// In case a slave ties awready := bready or wready := bready, we need this queue
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out_b <> Queue(out.b, depth, flow=combinational)
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// Sideband to track which transfers were the last fragment
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def sideband() = if (lite) {
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Module(new Queue(Bool(), maxInFlight, flow=combinational)).io
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} else {
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Module(new AXI4FragmenterSideband(maxInFlight, flow=combinational)).io
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}
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val sideband_ar_r = sideband()
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val sideband_aw_b = sideband()
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// AR flow control
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out_ar.valid := in_ar.valid && sideband_ar_r.enq.ready
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in_ar.ready := sideband_ar_r.enq.ready && out_ar.ready
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sideband_ar_r.enq.valid := in_ar.valid && out_ar.ready
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out_ar.bits := in_ar.bits
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sideband_ar_r.enq.bits := ar_last
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// When does W channel start counting a new transfer
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val wbeats_latched = RegInit(Bool(false))
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val wbeats_ready = Wire(Bool())
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val wbeats_valid = Wire(Bool())
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when (wbeats_valid && wbeats_ready) { wbeats_latched := Bool(true) }
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when (out_aw.fire()) { wbeats_latched := Bool(false) }
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// AW flow control
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out_aw.valid := in_aw.valid && sideband_aw_b.enq.ready && (wbeats_ready || wbeats_latched)
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in_aw.ready := sideband_aw_b.enq.ready && out_aw.ready && (wbeats_ready || wbeats_latched)
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sideband_aw_b.enq.valid := in_aw.valid && out_aw.ready && (wbeats_ready || wbeats_latched)
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wbeats_valid := in_aw.valid && !wbeats_latched
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out_aw.bits := in_aw.bits
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sideband_aw_b.enq.bits := aw_last
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// We need to inject 'last' into the W channel fragments, count!
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val w_counter = RegInit(UInt(0, width = AXI4Parameters.lenBits+1))
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val w_idle = w_counter === UInt(0)
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val w_todo = Mux(w_idle, Mux(wbeats_valid, w_beats, UInt(0)), w_counter)
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val w_last = w_todo === UInt(1)
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w_counter := w_todo - out_w.fire()
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assert (!out_w.fire() || w_todo =/= UInt(0)) // underflow impossible
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// W flow control
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wbeats_ready := w_idle
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out_w.valid := in_w.valid && (!wbeats_ready || wbeats_valid)
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in_w.ready := out_w.ready && (!wbeats_ready || wbeats_valid)
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out_w.bits := in_w.bits
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out_w.bits.last := w_last
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// R flow control
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val r_last = out_r.bits.last
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in_r.valid := out_r.valid && (!r_last || sideband_ar_r.deq.valid)
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out_r.ready := in_r.ready && (!r_last || sideband_ar_r.deq.valid)
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sideband_ar_r.deq.ready := r_last && out_r.valid && in_r.ready
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in_r.bits := out_r.bits
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in_r.bits.last := r_last && sideband_ar_r.deq.bits
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// B flow control
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val b_last = sideband_aw_b.deq.bits
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in_b.valid := out_b.valid && sideband_aw_b.deq.valid && b_last
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out_b.ready := sideband_aw_b.deq.valid && (!b_last || in_b.ready)
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sideband_aw_b.deq.ready := out_b.valid && (!b_last || in_b.ready)
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in_b.bits := out_b.bits
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// Merge errors from dropped B responses
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val r_resp = Reg(UInt(width = AXI4Parameters.respBits))
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val resp = out_b.bits.resp | r_resp
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when (out_b.fire()) { r_resp := Mux(b_last, UInt(0), resp) }
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in_b.bits.resp := resp
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}
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}
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class AXI4FragmenterSideband(maxInFlight: Int, flow: Boolean = false) extends Module
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{
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val io = new QueueIO(Bool(), maxInFlight)
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io.count := UInt(0)
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val state = RegInit(Bool(false))
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val count = RegInit(UInt(0, width = log2Up(maxInFlight)))
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val idle = count === UInt(0)
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io.deq.bits := state
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io.deq.valid := !idle
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if (flow) {
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when (io.enq.valid) {
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io.deq.valid := Bool(true)
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when (idle) { io.deq.bits := io.enq.bits }
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}
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}
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io.enq.ready := idle || (state === io.enq.bits)
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when (io.enq.fire()) { state := io.enq.bits }
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count := count + io.enq.fire() - io.deq.fire()
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}
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object AXI4Fragmenter
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{
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// applied to the AXI4 source node; y.node := AXI4Fragmenter()(x.node)
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def apply(lite: Boolean = false, maxInFlight: Int = 32, combinational: Boolean = true)(x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = {
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val fragmenter = LazyModule(new AXI4Fragmenter(lite, maxInFlight, combinational))
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fragmenter.node := x
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fragmenter.node
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}
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}
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@ -42,6 +42,10 @@ case class AXI4SlavePortParameters(
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// Check that the link can be implemented in AXI4
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require (maxTransfer <= beatBytes * (1 << AXI4Parameters.lenBits))
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lazy val routingMask = AddressDecoder(slaves.map(_.address))
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def findSafe(address: UInt) = Vec(slaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
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def findFast(address: UInt) = Vec(slaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
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// Require disjoint ranges for addresses
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slaves.combinations(2).foreach { case Seq(x,y) =>
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x.address.foreach { a => y.address.foreach { b =>
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