From a6874c03f76c4d9c28d48a019c739f0b6bf3bd7d Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Wed, 15 Mar 2017 15:17:40 -0700
Subject: [PATCH] Remove DecoupledTLB

---
 src/main/scala/rocket/TLB.scala | 45 ---------------------------------
 1 file changed, 45 deletions(-)

diff --git a/src/main/scala/rocket/TLB.scala b/src/main/scala/rocket/TLB.scala
index 8d9043fb..ff6d843d 100644
--- a/src/main/scala/rocket/TLB.scala
+++ b/src/main/scala/rocket/TLB.scala
@@ -207,48 +207,3 @@ class TLB(entries: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreMod
     }
   }
 }
-
-class DecoupledTLB(entries: Int)(implicit edge: TLEdgeOut, p: Parameters) extends Module {
-  val io = new Bundle {
-    val req = Decoupled(new TLBReq).flip
-    val resp = Decoupled(new TLBResp)
-    val ptw = new TLBPTWIO
-  }
-
-  val req = Reg(new TLBReq)
-  val resp = Reg(new TLBResp)
-  val tlb = Module(new TLB(entries))
-
-  val s_idle :: s_tlb_req :: s_tlb_resp :: s_done :: Nil = Enum(Bits(), 4)
-  val state = Reg(init = s_idle)
-
-  when (io.req.fire()) {
-    req := io.req.bits
-    state := s_tlb_req
-  }
-
-  when (tlb.io.req.fire()) {
-    state := s_tlb_resp
-  }
-
-  when (state === s_tlb_resp) {
-    when (tlb.io.resp.miss) {
-      state := s_tlb_req
-    } .otherwise {
-      resp := tlb.io.resp
-      state := s_done
-    }
-  }
-
-  when (io.resp.fire()) { state := s_idle }
-
-  io.req.ready := state === s_idle
-
-  tlb.io.req.valid := state === s_tlb_req
-  tlb.io.req.bits := req
-
-  io.resp.valid := state === s_done
-  io.resp.bits := resp
-
-  io.ptw <> tlb.io.ptw
-}